Electrical Characterization of Advanced Gate Dielectrics for Scaled CMOS Technology

2019 ◽  
Vol 8 (1) ◽  
pp. 93-98
Author(s):  
T.P. Ma
Keyword(s):  
Gate Dielectrics ◽  
Electrical Characterization ◽  
Cmos Technology ◽  
Scaled Cmos

Analysis of an Anomalous Transistor Exhibiting Dual-Vt Characteristics and Its Cause in a 90nm Node CMOS Technology

2012 ◽  
Author(s):  
Yuk L. Tsang ◽  
Xiang D. Wang ◽  
Reyhan Ricklefs ◽  
Jason Goertz
Keyword(s):  
Threshold Voltage ◽  
Electrical Characterization ◽  
Cmos Technology ◽  
Short Channel ◽  
Visual Defect ◽  
Subthreshold Region ◽  
Short Channel Effect ◽  
Channel Effect ◽  
Transistor Model

Abstract In this paper, we report a transistor model that has successfully led to the identification of a non visual defect. This model was based on detailed electrical characterization of a MOS NFET exhibiting a threshold voltage (Vt) of just about 40mv lower than normal. This small Vt delta was based on standard graphical extrapolation method in the usual linear Id-Vg plots. We observed, using a semilog plot, two slopes in the Id-Vg curves with Vt delta magnified significantly in the subthreshold region. The two slopes were attributed to two transistors in parallel with different Vts. We further found that one of the parallel transistors had short channel effect due to a punch-through mechanism. It was proposed and ultimately confirmed the cause was due to a dopant defect using scanning capacitance microscopy (SCM) technique.

Electrical Characterization of Oxynitrided Gate Dielectrics under Constant‐Current Fowler‐Nordheim Stress

1997 ◽  
Vol 144 (9) ◽  
pp. 3299-3304 ◽  
Author(s):  
T. K. Nguyen ◽  
L. M. Landsberger ◽  
S. Belkouch ◽  
C. Jean
Keyword(s):  
Gate Dielectrics ◽  
Electrical Characterization ◽  
Constant Current

Process and Manufacturing Challenges for High-K Gate Stack Systems

1999 ◽  
Vol 567 ◽  
Author(s):  
M.C. Gilmer ◽  
T-Y Luo ◽  
H.R. Huff ◽  
M.D. Jackson ◽  
S. Kim ◽  
...  
Keyword(s):  
Silicon Surface ◽  
Gate Dielectrics ◽  
Electrical Characterization ◽  
Metal Electrode ◽  
Significant Variable ◽  
Tem Analysis ◽  
Physical Mechanisms ◽  
High K ◽  
Commercial Equipment

ABSTRACTA design-of-experiments methodology was implemented to assess the commercial equipment viability to fabricate the high-K dielectrics Ta2O5, TiO2 and BST (70/30 and 50/50 compositions) for use as gate dielectrics. The high-K dielectrics were annealed in 100% or 10% O2 for different times and temperatures in conjunction with a previously prepared NH3 nitrided or 14N implanted silicon surface. Five metal electrode configurations—Ta, TaN, W, WN and TiN—were concurrently examined. Three additional silicon surface configurations were explored in conjunction with a more in-depth set of time and temperature anneals for Ta2O5. Electrical characterization of capacitors fabricated with the above high-K gate dielectrics, as well as SIMS and TEM analysis, indicate that the post high-K deposition annealing temperature was the most significant variable impacting the leakage current density, although there was minimal influence on the capacitance. Further studies are required, however, to clarify the physical mechanisms underlying the electrical data presented.

Evaluation Of 2.0 nm Grown and Deposited Dielectrics in 0.1 μm PMOSFETs

1998 ◽  
Vol 525 ◽  
Author(s):  
A. Srivastava ◽  
H. H. Heinisch ◽  
E. Vogel ◽  
C. Parker ◽  
C. M. Osburn ◽  
...  
Keyword(s):  
Gate Dielectrics ◽  
Electrical Characterization ◽  
Deposition Process ◽  
Gate Oxides ◽  
Boron Doped ◽  
Excellent Control ◽  
Lower Temperature ◽  
Boron Penetration

ABSTRACTThe quality and composition of ultra-thin 2.0 nm gate dielectrics advocated for the 0.1 μm technology regime is expected to significantly impact gate tunneling currents, P+-gate dopant depletion effects and boron penetration into the substrate in PMOSFETs. This paper presents a comparative assessment of alternative grown and deposited gate dielectrics in sub-micron fabricated devices. High quality rapid-thermal CVD oxides and oxynitrides are examined as alternatives to conventional furnace grown gate oxides. An alternative gate process using in-situ boron doped and RTCVD deposited poly-Si is explored. PMOSFETs with Leff down to 0.06 μm were fabricated using a 0.1 μm technology. Electrical characterization of fabricated devices revealed excellent control of gate-boron depletion with the in-situ gate deposition process in all devices. Boron penetration of 2.0 nm gate oxides was effectively controlled by the use of a lower temperature RTA process. The direct tunneling leakage, although significant at these thicknesses, was less than 1 mA/cm2 at Vd = −1.2 V for all dielectrics. MOSFETs with comparable drive currents and excellent junction and off-state leakages were obtained with each dielectric.

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