Process Technology for High-Resolution AM-PLED Displays on Flexible Metal Foil Substrates

2019 ◽  
Vol 3 (8) ◽  
pp. 349-359
Author(s):  
Ta-Ko Chuang ◽  
Matias Troccoli ◽  
Po-Chin Kuo ◽  
Abbas Jamshidi Roudbari ◽  
Miltiadis Hatalis ◽  
...  
Keyword(s):  
High Resolution ◽  
Metal Foil ◽  
Process Technology ◽  
Flexible Metal

Process Technology for High-Resolution AM-PLED Displays on Flexible Metal-Foil Substrates

2007 ◽  
Vol 10 (8) ◽  
pp. J92 ◽  
Author(s):  
T.-K. Chuang ◽  
M. Troccoli ◽  
P.-C. Kuo ◽  
A. Jamshidi-Roudbari ◽  
M. Hatalis ◽  
...  
Keyword(s):  
High Resolution ◽  
Metal Foil ◽  
Process Technology ◽  
Flexible Metal

Synthesis of CdTe thin films on flexible metal foil by electrodeposition

2016 ◽  
Vol 122 (4) ◽  
Author(s):  
H. Luo ◽  
L. G. Ma ◽  
W. M. Xie ◽  
Z. L. Wei ◽  
K. G. Gao ◽  
...  
Keyword(s):  
Thin Films ◽  
Metal Foil ◽  
Cdte Thin Films ◽  
Flexible Metal

Top-emitting 230dots∕in. active-matrix polymer light-emitting diode displays on flexible metal foil substrates

2007 ◽  
Vol 90 (15) ◽  
pp. 151114 ◽  
Author(s):  
Ta-Ko Chuang ◽  
Matias Troccoli ◽  
Po-Chin Kuo ◽  
Abbas Jamshidi-Roudbari ◽  
Miltiadis K. Hatalis ◽  
...  
Keyword(s):  
Light Emitting Diode ◽  
Metal Foil ◽  
Active Matrix ◽  
Light Emitting ◽  
Matrix Polymer ◽  
Polymer Light Emitting Diode ◽  
Flexible Metal

scholarly journals Doping of polycrystalline CdTe for high-efficiency solar cells on flexible metal foil

2013 ◽  
Vol 4 (1) ◽  
Author(s):  
Lukas Kranz ◽  
Christina Gretener ◽  
Julian Perrenoud ◽  
Rafael Schmitt ◽  
Fabian Pianezzi ◽  
...  
Keyword(s):  
Solar Cells ◽  
High Efficiency ◽  
Metal Foil ◽  
High Efficiency Solar Cells ◽  
Flexible Metal

Advanced Manufacturing Technology for Fan-Out Wafer Level Packaging

2015 ◽  
Vol 2015 (1) ◽  
pp. 000251-000255 ◽  
Author(s):  
Doug Shelton
Keyword(s):  
High Resolution ◽  
Mass Production ◽  
High Density ◽  
Advanced Manufacturing Technology ◽  
Successful Implementation ◽  
Advanced Manufacturing ◽  
Wafer Level ◽  
Process Technology ◽  
Key Technology ◽  
Wafer Level Packaging

Advanced process technology is required to develop and enable mass production of Fan-Out Wafer-Level Packaging (FOWLP) solutions for high-density 3D and 2.5D packaging. Canon has identified key challenges that must be solved for successful implementation of high-density integration technologies and has developed key technology for Canon Litho Systems to support the most challenging processes. In this paper, Canon will present process optimization results for high-resolution patterning of wafers across large topography as well as solutions that enable litho systems to compensate for FOWLP grid error due to die placement errors.

54.4: 4.1 inch Top-Emission AMOLED on Flexible Metal Foil

2005 ◽  
Vol 36 (1) ◽  
pp. 1642 ◽  
Author(s):  
Hyun Soo Shin ◽  
Jae Bon Koo ◽  
Jae Kyeong Jeong ◽  
Yeon Gon Mo ◽  
Ho Kyun Chung ◽  
...  
Keyword(s):  
Metal Foil ◽  
Flexible Metal

A CMOS Input Buffer for High-Resolution A/D Converters with High Sampling Rates

2014 ◽  
Vol 678 ◽  
pp. 497-500
Author(s):  
Xing Fa Huang ◽  
Rong Bin Hu ◽  
Liang Li
Keyword(s):  
High Resolution ◽  
Input Signal ◽  
High Speed ◽  
Process Technology ◽  
Input Buffer ◽  
Design And Implementation ◽  
High Linearity ◽  
High Sampling

With respect to the application of high-speed, high-resolution A/D converter, the design and implementation of a CMOS input buffer is introduced. The buffer features high-speed and high-linearity. Its performances have been verified in a 14-bit 250MSPS pipelined A/D converter which is developed in 0.18um CMOS-based process technology. The simulation shows that the SFDR of the buffer is up to 104dB at an input clock of 250MHz with an input signal of 25MHz.

High-Swing, High-Resolution, Low-Power, Low-Area Voltage-Mode LTA/WTA Circuits

2015 ◽  
Vol 24 (07) ◽  
pp. 1550103 ◽  
Author(s):  
Mohammad Soleimani ◽  
Siroos Toofan ◽  
Mostafa Yargholi
Keyword(s):  
High Resolution ◽  
Low Power ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Rank Order ◽  
Active Area ◽  
Total Power ◽  
Common Source ◽  
Cmos Process ◽  
Process Technology

In this paper, a general architecture for analog implementation of loser/winner-take-all (LTA/WTA) and other rank order circuits is presented. This architecture is composed of a differential amplifier with merged n-inputs and a merged common-source with active load (MCSAL) circuit to choose the desired input. The advantages of the proposed structure are simplicity, very high resolution, very low supply voltage requirements, very low output resistor, low power dissipation, low active area and simple expansion for multiple inputs by adding only three transistors for each extra input. The post-layout simulation results of proposed circuits are presented by HSPICE software in 0.35-μm CMOS process technology. The total power dissipation of proposed circuits is about 110-μW. Also, the total active area is about 550-μm2 for five-input proposed circuits, and would be negligibly increased for each extra input.

Characterization of Cu2ZnSnS4 thin films on flexible metal foil substrates

2014 ◽  
Vol 26 (2) ◽  
pp. 726-733 ◽  
Author(s):  
Jiaxiong Xu ◽  
Zhongming Cao ◽  
Yuanzheng Yang ◽  
Zhiwei Xie
Keyword(s):  
Thin Films ◽  
Metal Foil ◽  
Flexible Metal
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