High Performance, Ultra-thin, Strained-Ge, Heterostructure FETs With High Mobility And Low Leakage

2019 ◽  
Vol 3 (7) ◽  
pp. 687-695 ◽  
Author(s):  
Tejas Krishnamohan ◽  
Donghyun Kim ◽  
Yoshio Nishi ◽  
Krishna Saraswat ◽  
Christoph Jungemann
Keyword(s):  
High Performance ◽  
High Mobility ◽  
Low Leakage ◽  
Heterostructure Fets

CHASSIS DESIGN & PERFORMANCE ANALYSIS FOR THE EUROPEAN EXOMARS ROVER

2005 ◽  
Vol 29 (4) ◽  
pp. 507-517
Author(s):  
Alex Ellery ◽  
Lutz Richter ◽  
Reinhold Bertrand
Keyword(s):  
Performance Analysis ◽  
Weight Distribution ◽  
High Performance ◽  
High Mobility ◽  
Scientific Instrument ◽  
Equal Weight ◽  
Scientific Instruments ◽  
Design Issues ◽  
Martian Surface ◽  
Considerable Size

The European Space Agency’s (ESA) ExoMars rover has recently been subject to a Phase A study led by EADS Astrium, UK. This rover mission represents a highly ambitious venture in that the rover is of considerable size ~200+kg with high mobility carrying a highly complex scientific instrument suite (Pasteur) of up to 40 kg in mass devoted to exobiological investigation of the Martian surface and sub-surface. The chassis design has been a particular challenge given the inhospitable terrain on Mars and the need to traverse such terrain robustly in order to deliver the scientific instruments to science targets of exobiological interest, We present some of the results and design issues encountered during the Phase A study related to the chassis. In particular, we have focussed on the overall tractive performance of a number of candidate chassis designs and selected the RCL (Science & Technology Rover Company Ltd in Russian) concept C design as the baseline option in terms of high performance with minimal mechanical complexity overhead. This design is a six-wheeled double-rocker bogie design to provide springless suspension and maintain approximately equal weight distribution across each wheel.

scholarly journals Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Aryan Afzalian
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
High Mobility ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Grand Challenge ◽  
Gate Length ◽  
Delay Performance ◽  
Effect Transistor

AbstractUsing accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

Quaternisation-polymerized N-type polyelectrolytes: synthesis, characterisation and application in high-performance polymer solar cells

2017 ◽  
Vol 4 (1) ◽  
pp. 88-97 ◽  
Author(s):  
Zhicheng Hu ◽  
Rongguo Xu ◽  
Sheng Dong ◽  
Kai Lin ◽  
Jinju Liu ◽  
...  
Keyword(s):  
Solar Cells ◽  
High Performance ◽  
Polymer Solar Cells ◽  
High Mobility ◽  
High Performance Polymer

We design and synthesize a series of high-mobility n-type polyelectrolytes with different anions via quaternisation polymerisation, which can be utilized as thickness-insensitive electron-transporting materials for polymer solar cells.

Development of high k/III-V (InGaAs, InAs, InSb) structures for future low power, high speed device applications

2013 ◽  
Vol 1538 ◽  
pp. 291-302
Author(s):  
Edward Yi Chang ◽  
Hai-Dang Trinh ◽  
Yueh-Chin Lin ◽  
Hiroshi Iwai ◽  
Yen-Ku Lin
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
High Speed ◽  
High Performance ◽  
Gate Oxide ◽  
Chemical Cleaning ◽  
Low Leakage ◽  
Low Leakage Current ◽  
High K ◽  
Cleaning Methods

ABSTRACTIII-V compounds such as InGaAs, InAs, InSb have great potential for future low power high speed devices (such as MOSFETs, QWFETs, TFETs and NWFETs) application due to their high carrier mobility and drift velocity. The development of good quality high k gate oxide as well as high k/III-V interfaces is prerequisite to realize high performance working devices. Besides, the downscaling of the gate oxide into sub-nanometer while maintaining appropriate low gate leakage current is also needed. The lack of high quality III-V native oxides has obstructed the development of implementing III-V based devices on Si template. In this presentation, we will discuss our efforts to improve high k/III-V interfaces as well as high k oxide quality by using chemical cleaning methods including chemical solutions, precursors and high temperature gas treatments. The electrical properties of high k/InSb, InGaAs, InSb structures and their dependence on the thermal processes are also discussed. Finally, we will present the downscaling of the gate oxide into sub-nanometer scale while maintaining low leakage current and a good high k/III-V interface quality.

scholarly journals Orthogonal Time Sequency Multiplexing Modulation

2021 ◽  
Author(s):  
Tharaj Thaj ◽  
Emanuele Viterbo
Keyword(s):  
Time Domain ◽  
Orthogonal Frequency Division Multiplexing ◽  
High Performance ◽  
High Mobility ◽  
Low Complexity ◽  
Modulation Scheme ◽  
Frequency Space ◽  
Time Frequency ◽  
Single Carrier ◽  
The Time Domain

This paper proposes <i>orthogonal time sequency multiplexing</i> (OTSM), a novel single carrier modulation scheme based on the well known Walsh-Hadamard transform (WHT) combined with row-column interleaving, and zero padding (ZP) between blocks in the time-domain. The information symbols in OTSM are multiplexed in the delay and sequency domain using a cascade of time-division and Walsh-Hadamard (sequency) multiplexing. By using the WHT for transmission and reception, the modulation and demodulation steps do not require any complex multiplications. We then propose two low-complexity detectors: (i) a simpler non-iterative detector based on a single tap minimum mean square time-frequency domain equalizer and (ii) an iterative time-domain detector. We demonstrate, via numerical simulations, that the proposed modulation scheme offers high performance gains over orthogonal frequency division multiplexing (OFDM) and exhibits the same performance of orthogonal time frequency space (OTFS) modulation, but with lower complexity. In proposing OTSM, along with simple detection schemes, we offer the lowest complexity solution to achieving reliable communication in high mobility wireless channels, as compared to the available schemes published so far in the literature.

Analysis and Simulation of a Low-Leakage Analog Single Gate and FinFET Circuits

2014 ◽  
Vol 13 (02) ◽  
pp. 1450012 ◽  
Author(s):  
Manorama Chauhan ◽  
Ravindra Singh Kushwah ◽  
Pavan Shrivastava ◽  
Shyam Akashe
Keyword(s):  
Integrated Circuits ◽  
Metal Oxide ◽  
Low Power ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Short Channel ◽  
State Dependency ◽  
Low Leakage

In the world of Integrated Circuits, complementary metal–oxide–semiconductor (CMOS) has lost its ability during scaling beyond 50 nm. Scaling causes severe short channel effects (SCEs) which are difficult to suppress. FinFET devices undertake to replace usual Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) because of their better ability in controlling leakage and diminishing SCEs while delivering a strong drive current. In this paper, we present a relative examination of FinFET with the double gate MOSFET (DGMOSFET) and conventional bulk Si single gate MOSFET (SGMOSFET) by using Cadence Virtuoso simulation tool. Physics-based numerical two-dimensional simulation results for FinFET device, circuit power is presented, and classifying that FinFET technology is an ideal applicant for low power applications. Exclusive FinFET device features resulting from gate–gate coupling are conversed and efficiently exploited for optimal low leakage device design. Design trade-off for FinFET power and performance are suggested for low power and high performance applications. Whole power consumptions of static and dynamic circuits and latches for FinFET device, believing state dependency, show that leakage currents for FinFET circuits are reduced by a factor of over ~ 10X, compared to DGMOSFET and ~ 20X compared with SGMOSFET.

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