Comparison of SiGe Virtual Substrates for the Fabrication of Strained Silicon-on-Insulator (sSOI) Using Wafer Bonding and Layer Transfer

2019 ◽  
Vol 3 (7) ◽  
pp. 317-324 ◽  
Author(s):  
Manfred Reiche ◽  
Ionut Radu ◽  
Cameliu Himcinschi ◽  
Rajendra Singh ◽  
Silke Christiansen ◽  
...  
Keyword(s):  
Wafer Bonding ◽  
Silicon On Insulator ◽  
Strained Silicon ◽  
Layer Transfer

Compressive uniaxially strained silicon on insulator by prestrained wafer bonding and layer transfer

2007 ◽  
Vol 90 (23) ◽  
pp. 231909 ◽  
Author(s):  
C. Himcinschi ◽  
M. Reiche ◽  
R. Scholz ◽  
S. H. Christiansen ◽  
U. Gösele
Keyword(s):  
Wafer Bonding ◽  
Silicon On Insulator ◽  
Strained Silicon ◽  
Layer Transfer

Strained Silicon On Insulator wafers made by the Smart Cut™ technology

2004 ◽  
Vol 809 ◽  
Author(s):  
B. Ghyselen ◽  
Y. Bogumilowicz ◽  
C. Aulnette ◽  
A. Abbadie ◽  
B. Osternaud ◽  
...  
Keyword(s):  
Thin Films ◽  
Hole Mobility ◽  
Silicon On Insulator ◽  
Strained Silicon ◽  
Layer Transfer ◽  
Strained Si ◽  
Engineered Substrates

ABSTRACTStrained Silicon On Insulator wafers are today envisioned as a natural and powerfulenhancement to standard SOI and/or bulk-like strained Si layers. For MOSFETs applications, thisnew technology potentially combines enhanced devices scalability allowed by thin films andenhanced electron and hole mobility in strained silicon. This paper is intended to demonstrate byexperimental results how a layer transfer technique such as the Smart Cut™ technology can be usedto obtain good quality tensile Strained Silicon On insulator wafers. Detailed experiments andcharacterizations will be used to characterize these engineered substrates and show that they arecompatible with the applications.

Formation of III-V Semiconductor Engineered Substrates Using Smart CutTM Layer Transfer Technology

2008 ◽  
Vol 1068 ◽  
Author(s):  
Fabrice Jerome Letertre
Keyword(s):  
Wafer Bonding ◽  
Dominant Role ◽  
Dissimilar Materials ◽  
Current Drive ◽  
Thin Layers ◽  
Silicon On Insulator ◽  
Layer Transfer ◽  
Semiconductor Wafer ◽  
Substrate Engineering ◽  
Engineered Substrates

ABSTRACTEngineered substrates are expected to play a dominant role in the field of modern nano-electronic and optoelectronic technologies. For example, engineered substrates like SOI (Silicon On Insulator) make possible efficient optimization of transistors' current drive while minimizing the leakage and reducing parasitic elements, thus enhancing the overall IC performance in terms of speed or power consumption. Other generations of engineered substrates like strained SOI (sSOI) provide solutions to traditional scaling for 32 nm node and beyond [1] technologies.The Smart Cutä technology, introduced in the mid 1990's by M. Bruel [2] is a revolutionnary and powerful thin film technology for bringing to industrial maturity engineered substrate solutions. It is a combination of wafer bonding and layer transfer via the use of ion implantation. It allows multiple high quality transfers of thin layers, from a single crystal donor wafer onto another substrate of a different nature, allowing the integration of dissimilar materials. As a consequence, it opens the path to the formation of III-V based engineered substrates by integrating, for example, materials like GaAs [3], InP [4], SiC [5], GaN [6], Germanium [7] ,and Si [8 ]on a silicon, poly SiC, sapphire, ceramic, or metal substrates?In this paper, we will review the current wafer bonding and layer transfer technologies with a special emphasis on the Smart Cut technology applied to compound semiconductors. Beyond SOI, the innovation provided by substrate engineering will be illustrated by the case of Silicon and SiC engineered substrate serving as a platform for GaN and related alloys processing [9,10,11,12] as well as the case of Germanium/Si platform for the growth of GaAs/InP materials, opening the path to Si CMOS and III-V microelectronics/ optoelectronics functions hybrid integration [13, 14]. Recent results obtained in these two focused areas will be presented to emphasize the added functionalities offered by engineered substrates.[1] B. Ghyselen et al., ICSI3 proc., 173 5 (2003)[2] M. Bruel et al., Electron. Lett., vol 31, p. 1201 (1995)[3] E. Jalaguier et al., Electron. Lett., 34(4), 408 (1998)[4] E. Jalaguier et al. Proc. llth Intern. Conf. on InP and Related Materials, Davos, Switzerland, (1999)[5] L. Di Cioccio et al., Mat. Sci. and Eng. B Vol. 46, p. 349 (1997)[6] A. Tauzin and al., Semiconductor Wafer Bonding VIII, ECS Proc Vol. 2005-02, pp. 119-127[7] F. Letertre, et al. MRS Symp. Proc., 809, B4.4 (2004).[8] B. Faure et al., Semiconductor Wafer Bonding VIII, ECS Proc Vol. 2005-02, pp. 106-118[9] H. Larèche et al., Mat. Sci. For., Vols. 457–460 pp.. 1621 – 1624 (2004)[10] G. Meneghesso et al , IEDM 2007, to be published[11] Y. Dikme et al., Journal of Crystal Growth, v.272 (1-4), pp. 500-505 (2004)[12] J. Dorsaz and al., Proceedings, ICNS6 (2005)[13] S.G. Thomas et al., IEEE EDL Vol. 26, July 2005.[14] K. Chilukuri, Semi. Sci. Technol. 22 (2007) 29-34

Uniaxially strained silicon by wafer bonding and layer transfer

2007 ◽  
Vol 51 (2) ◽  
pp. 226-230 ◽  
Author(s):  
C. Himcinschi ◽  
I. Radu ◽  
F. Muster ◽  
R. Singh ◽  
M. Reiche ◽  
...  
Keyword(s):  
Wafer Bonding ◽  
Strained Silicon ◽  
Layer Transfer

Beyond “Smart-Cut®” Recent Advances in Layer Transfer for Material Integration

MRS Bulletin ◽  
1998 ◽  
Vol 23 (12) ◽  
pp. 40-44 ◽  
Author(s):  
Q-Y. Tong ◽  
R.W. Bower
Keyword(s):  
Wafer Bonding ◽  
Dissimilar Materials ◽  
Thin Layers ◽  
Silicon On Insulator ◽  
Material Structure ◽  
Layer Transfer ◽  
Single Chip ◽  
Lattice Constants ◽  
Original Surface ◽  
Compliant Substrates

An integrated substrate, consisting of more than one material or material structure, is highly desirable for optimizing performance of multiple-device types on a single chip or for growing high-quality heteroepitaxial films on compliant substrates. A typical integrated substrate contains a stack of thin layers of similar or dissimilar materials that are either amorphous, or poly- or single-crystalline with a variety of lattice constants or crystallographic orientations. Partially or fully processed device layers can also be transferred onto a desired substrate where the transferred device layer can be further processed on the opposite side of its original surface. In this article, we focus on issues related to layer transfer for material integration.Layer transfer from a hydrogen (H)-implanted wafer onto a desired substrate by wafer bonding and layer splitting (the so-called “Smart-Cut®” method) is an attractive approach to prepare integrated materials, such as-silicon-on-insulator (SOI), SiC or GaAs on oxidized silicon, and Ge on glass.

High-quality crystalline layer transfer from a silicon-on-insulator substrate onto a sapphire substrate using wafer bonding

2003 ◽  
Vol 32 (11) ◽  
pp. 1339-1343 ◽  
Author(s):  
D. V. Singh ◽  
L. Shi ◽  
K. W. Guarini ◽  
P. M. Mooney ◽  
S. J. Koester ◽  
...  
Keyword(s):  
Sapphire Substrate ◽  
Wafer Bonding ◽  
Silicon On Insulator ◽  
Layer Transfer ◽  
High Quality ◽  
Crystalline Layer ◽  
Insulator Substrate
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