Charge Trapping Characteristics of W-La2O3-nSi MIS Capacitors After Post-Metallization Annealing PMA in N2

2019 ◽  
Vol 3 (3) ◽  
pp. 233-244 ◽  
Author(s):  
Joel Molina ◽  
Kiichi Tachi ◽  
Kuniyuki Kakushima ◽  
Parhat Ahmet ◽  
Kazuo Tsutsui ◽  
...  
Keyword(s):  
Charge Trapping ◽  
Mis Capacitors

Reduction of CV Hysteresis in Metal/High-k MISFETs Using Flash Lamp Post Deposition Annealing

2004 ◽  
Vol 811 ◽  
Author(s):  
Takeo Matsuki ◽  
Yasushi Akasaka ◽  
Kiyoshi Hayashi ◽  
Masataka Noguchi ◽  
Koji Yamashita ◽  
...  
Keyword(s):  
Charge Trapping ◽  
Gate Insulator ◽  
Flash Lamp ◽  
Gate Electrode ◽  
Post Deposition Annealing ◽  
Hysteresis Width ◽  
High K ◽  
Mis Capacitors ◽  
Hysteresis Characteristics ◽  
Post Deposition

ABSTRACTA Xe flash lamp (FL) heating technique was applied to the post deposition annealing process (PDA) for HfAlOx/SiO2 gate insulator with poly-Si or W/TiN gate electrode in a gate last based process. In the case of W/TiN/HfAlOx/SiO2, CV hysteresis with less than 10mV was achieved using the FL-PDA. However, the FL-PDA increased hysteresis width up to over 100 mV when poly-Si was used as a gate electrode. That occurred also with low temperature (700 °C) rapid thermal PDA process. The lower thermal budget achieved by the flash lamp annealing and the metal gate is effective to suppress the interfacial reaction which causes the traps responsible for the hysteresis. Charge trapping in the W/TiN/HfAlOx/SiO2 was evaluated using CV hysteresis characteristics in the MISFETs and the MIS capacitors. Electron was major trapped charge of the HfAlOx.

scholarly journals Effect of blocking and tunnel oxide layers on the charge trapping properties of MIS capacitors with ALD HfO2/Al2O3 nanolaminated films

2021 ◽  
Vol 1762 (1) ◽  
pp. 012038
Author(s):  
D Spassov ◽  
A Paskaleva ◽  
E Guziewicz ◽  
W Wozniak ◽  
T Stanchev ◽  
...  
Keyword(s):  
Charge Trapping ◽  
Oxide Layers ◽  
Mis Capacitors

An Investigation of Capacitance-Voltage Hysteresis in Al2O3/SiC MIS Capacitors

2015 ◽  
Vol 821-823 ◽  
pp. 516-519 ◽  
Author(s):  
Yi Yu Wang ◽  
Xiao Lei Wang ◽  
Cheng Zhan Li ◽  
Jia Wu ◽  
Lin Chao Han ◽  
...  
Keyword(s):  
Electric Field ◽  
Charge Trapping ◽  
Oxide Semiconductor ◽  
Semiconductor Interface ◽  
Charge Model ◽  
Capacitance Voltage ◽  
Sheet Charge ◽  
Maximum Electric Field ◽  
Mis Capacitors ◽  
Mos Structures

Charge trapping behavior in Al2O3/SiC MOS structures was investigated by C-V hysteresis measurements in combination with XPS analysis. According to the quadratic fit of C-V hysteresis vs. tox curves, the density of the injected charges in the bulk Al2O3 films are the same under different maximum electric field, while the density of sheet charges increase with the increase of maximum electric field. Thus, a simple sheet charge model has been used to evaluate the actual effect of the electron injection phenomenon. The charge trapping levels can be as high as 1013 cm-2, indicating the importance of C-V hysteresis in Al2O3/SiC structures. All the trapping charges are found to be located at a distance ranging from 3 to 4 nm from the interface. Furthermore, no detectable interface oxide between Al2O3 and SiC has been found through our XPS measurements. We conclude that the origin of charge trapping sites in Al2O3/SiC structures is the native defects in ALD Al2O3 layer and predominantly the border traps in the Al2O3 near the oxide/semiconductor interface.

High-k MNOS-Like Stacked Dielectrics for Non-Volatile Memory Application

2016 ◽  
Vol 39 ◽  
pp. 121-133
Author(s):  
Larysa Khomenkova ◽  
Pascal Normand ◽  
Fabrice Gourbilleau ◽  
Abdelilah Slaoui ◽  
Caroline Bonafos
Keyword(s):  
Electrical Characterization ◽  
Charge Trapping ◽  
Flat Band ◽  
Carrier Injection ◽  
High K ◽  
Structural And Electrical Properties ◽  
Non Volatile Memory ◽  
High Resolution Tem ◽  
Mis Capacitors ◽  
Dielectric Structures

Charge-trapping memories such as SONOS and MONOS have attracted considerable attention as promising alternatives for next-generation flash memories due to dielectric layer’s scalability, process simplicity, power economy, operation versatility. Nevertheless, the continued miniaturization of the devices forces an application of high-k dielectrics. In this work high-k stacked dielectric structures based on the combination of Hf-based and SiNx materials were fabricated. Their structural and electrical properties versus deposition conditions are studied by means of FTIR-ATR and high-resolution TEM techniques. All samples demonstrated smooth surface (roughness below 1 nm) and abrupt interfaces between the different stacked layers. No crystallization of Hf-based layers was observed after annealing at 800°C for 30 min, demonstrating their amorphous nature and phase stability upon annealing. Electrical characterization was carried out for all samples through capacitance-voltage (C-V) measurements of MIS capacitors. Uniform C-V characteristics were measured along the samples for all stacks. Besides, significant flat-band hysteresis due to charging of the stacks caused by carrier injection from the substrate was observed for the structures with pure HfO2 layers.

scholarly journals The Characteristics of Transparent Non-Volatile Memory Devices Employing Si-Rich SiOX as a Charge Trapping Layer and Indium-Tin-Zinc-Oxide

Nanomaterials ◽  
2019 ◽  
Vol 9 (5) ◽  
pp. 784 ◽  
Author(s):  
Joong-Hyun Park ◽  
Myung-Hun Shin ◽  
Jun-Sin Yi
Keyword(s):  
Zinc Oxide ◽  
Gate Voltage ◽  
Voltage Pulse ◽  
Charge Trapping ◽  
Memory Window ◽  
Logic Devices ◽  
Non Volatile Memory ◽  
Sweep Voltage ◽  
Mis Capacitors ◽  
Bottom Gate

We fabricated the transparent non-volatile memory (NVM) of a bottom gate thin film transistor (TFT) for the integrated logic devices of display applications. The NVM TFT utilized indium–tin–zinc–oxide (ITZO) as an active channel layer and multi-oxide structure of SiO2 (blocking layer)/Si-rich SiOX (charge trapping layer)/SiOXNY (tunneling layer) as a gate insulator. The insulators were deposited using inductive coupled plasma chemical vapor deposition, and during the deposition, the trap states of the Si-rich SiOx charge trapping layer could be controlled to widen the memory window with the gas ratio (GR) of SiH4:N2O, which was confirmed by fourier transform infrared spectroscopy (FT-IR). We fabricated the metal–insulator–silicon (MIS) capacitors of the insulator structures on n-type Si substrate and demonstrated that the hysteresis capacitive curves of the MIS capacitors were a function of sweep voltage and trap density (or GR). At the GR6 (SiH4:N2O = 30:5), the MIS capacitor exhibited the widest memory window; the flat band voltage (ΔVFB) shifts of 4.45 V was obtained at the sweep voltage of ±11 V for 10 s, and it was expected to maintain ~71% of the initial value after 10 years. Using the Si-rich SiOX charge trapping layer deposited at the GR6 condition, we fabricated a bottom gate ITZO NVM TFT showing excellent drain current to gate voltage transfer characteristics. The field-effect mobility of 27.2 cm2/Vs, threshold voltage of 0.15 V, subthreshold swing of 0.17 V/dec, and on/off current ratio of 7.57 × 107 were obtained at the initial sweep of the devices. As an NVM, ΔVFB was shifted by 2.08 V in the programing mode with a positive gate voltage pulse of 11 V and 1 μs. The ΔVFB was returned to the pristine condition with a negative voltage pulse of −1 V and 1 μs under a 400–700 nm light illumination of ~10 mWcm−2 in erasing mode, when the light excites the electrons to escape from the charge trapping layer. Using this operation condition, ~90% (1.87 V) of initial ΔVFB (2.08 V) was expected to be retained over 10 years. The developed transparent NVM using Si-rich SiOx and ITZO can be a promising candidate for future display devices integrating logic devices on panels.

Reduction of Charge Trapping Sites in Al2O3/SiO2 Stacked Gate Dielectrics by Incorporating Nitrogen for Highly Reliable 4H-SiC MIS Devices

2011 ◽  
Vol 679-680 ◽  
pp. 496-499 ◽  
Author(s):  
Takuji Hosoi ◽  
Yusuke Kagei ◽  
Takashi Kirino ◽  
Shuhei Mitani ◽  
Yuki Nakano ◽  
...  
Keyword(s):  
Gate Dielectrics ◽  
Field Effect Transistors ◽  
Pure Aluminum ◽  
Charge Trapping ◽  
Aluminum Oxynitride ◽  
Al2o3 Film ◽  
Flatband Voltage ◽  
Mis Devices ◽  
Mis Capacitors ◽  
Trapping Sites

Superior flatband voltage (Vfb) stability of SiC-based metal-insulator-semiconductor (MIS) devices with aluminum oxynitride (AlON) gate dielectrics was demonstrated. MIS capacitors with gate insulators consisting of a thick pure aluminum oxide (Al2O3) and a thin underlying SiO2 layer fabricated on n-type 4H-SiC substrates showed a positive Vfb shift due to substrate electron injection depending on the applied gate bias and the thickness of the SiO2 interlayer. This large Vfb shift was greatly suppressed for devices with AlON/SiO2 stacked gate dielectrics, suggesting that electron trapping sites in Al2O3 film were mostly compensated for by nitrogen incorporation. This finding is helpful in realizing highly reliable SiC-based MIS field-effect-transistors (MISFETs) in terms of threshold voltage stability.

Charge Trapping and Degradation Properties of PZT Thin Films for MEMS

1996 ◽  
Vol 444 ◽  
Author(s):  
Hyeon-Seag Kim ◽  
D. L. Polla ◽  
S. A. Campbell
Keyword(s):  
Thin Films ◽  
Loss Factor ◽  
High Field ◽  
Microelectromechanical Systems ◽  
Charge Trapping ◽  
Metal Organic ◽  
Electrical Reliability ◽  
Silicon Based ◽  
Degradation Properties ◽  
Organic Decomposition

AbstractThe electrical reliability properties of PZT (54/46) thin films have been measured for the purpose of integrating this material with silicon-based microelectromechanical systems. Ferroelectric thin films of PZT were prepared by metal organic decomposition. The charge trapping and degradation properties of these thin films were studied through device characteristics such as hysteresis loop, leakage current, fatigue, dielectric constant, capacitancevoltage, and loss factor measurements. Several unique experimental results have been found. Different degradation processes were verified through fatigue (bipolar stress), low and high charge injection (unipolar stress), and high field stressing (unipolar stress).

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