Electrical Characterization of 13 A In Situ Steam-Generated Oxynitride Gate Dielectrics

2006 ◽  
Vol 9 (2) ◽  
pp. G66-G68 ◽  
Author(s):  
T.-M. Pan
1998 ◽  
Vol 525 ◽  
Author(s):  
A. Srivastava ◽  
H. H. Heinisch ◽  
E. Vogel ◽  
C. Parker ◽  
C. M. Osburn ◽  
...  

ABSTRACTThe quality and composition of ultra-thin 2.0 nm gate dielectrics advocated for the 0.1 μm technology regime is expected to significantly impact gate tunneling currents, P+-gate dopant depletion effects and boron penetration into the substrate in PMOSFETs. This paper presents a comparative assessment of alternative grown and deposited gate dielectrics in sub-micron fabricated devices. High quality rapid-thermal CVD oxides and oxynitrides are examined as alternatives to conventional furnace grown gate oxides. An alternative gate process using in-situ boron doped and RTCVD deposited poly-Si is explored. PMOSFETs with Leff down to 0.06 μm were fabricated using a 0.1 μm technology. Electrical characterization of fabricated devices revealed excellent control of gate-boron depletion with the in-situ gate deposition process in all devices. Boron penetration of 2.0 nm gate oxides was effectively controlled by the use of a lower temperature RTA process. The direct tunneling leakage, although significant at these thicknesses, was less than 1 mA/cm2 at Vd = −1.2 V for all dielectrics. MOSFETs with comparable drive currents and excellent junction and off-state leakages were obtained with each dielectric.


AIP Advances ◽  
2014 ◽  
Vol 4 (11) ◽  
pp. 117126 ◽  
Author(s):  
L. Arzubiaga ◽  
F. Golmar ◽  
R. Llopis ◽  
F. Casanova ◽  
L. E. Hueso

1997 ◽  
Vol 144 (9) ◽  
pp. 3299-3304 ◽  
Author(s):  
T. K. Nguyen ◽  
L. M. Landsberger ◽  
S. Belkouch ◽  
C. Jean

1999 ◽  
Vol 567 ◽  
Author(s):  
M.C. Gilmer ◽  
T-Y Luo ◽  
H.R. Huff ◽  
M.D. Jackson ◽  
S. Kim ◽  
...  

ABSTRACTA design-of-experiments methodology was implemented to assess the commercial equipment viability to fabricate the high-K dielectrics Ta2O5, TiO2 and BST (70/30 and 50/50 compositions) for use as gate dielectrics. The high-K dielectrics were annealed in 100% or 10% O2 for different times and temperatures in conjunction with a previously prepared NH3 nitrided or 14N implanted silicon surface. Five metal electrode configurations—Ta, TaN, W, WN and TiN—were concurrently examined. Three additional silicon surface configurations were explored in conjunction with a more in-depth set of time and temperature anneals for Ta2O5. Electrical characterization of capacitors fabricated with the above high-K gate dielectrics, as well as SIMS and TEM analysis, indicate that the post high-K deposition annealing temperature was the most significant variable impacting the leakage current density, although there was minimal influence on the capacitance. Further studies are required, however, to clarify the physical mechanisms underlying the electrical data presented.


2009 ◽  
Vol 419-420 ◽  
pp. 21-24
Author(s):  
Ming Chang ◽  
Chia Hung Lin ◽  
Chung Po Lin ◽  
Juti Rani Deka

With rapid expansion of nanotechnology, microminiaturization has become imperative in the field of micro/nano fabrication. A nanomanipulation system with high degrees of freedom that can perform nanomachining, nanofabrication and mechanical/electrical characterization of nanoscale objects inside a scanning electron microscope (SEM) is presented. The manipulation system consists of several individual operating units each having three linear stages and one rotational stage. The body of the manipulator is designed using the idea of superposition. Each operating unit can move in the permissible range of SEM’s vacuum chamber and can increase or decrease the number of units according to the requirement. Experiments were executed to investigate the in-situ electrical resistance of nano materials.


2013 ◽  
Vol 19 (S2) ◽  
pp. 456-457
Author(s):  
M. Rudneva ◽  
T. Kozlova ◽  
H.W. Zandbergen

Extended abstract of a paper presented at Microscopy and Microanalysis 2013 in Indianapolis, Indiana, USA, August 4 – August 8, 2013.


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