Control of the Interfacial Layer Thickness in Hafnium Oxide Gate Dielectric Grown by PECVD

2003 ◽  
Vol 150 (4) ◽  
pp. F75 ◽  
Author(s):  
Kyu-Jeong Choi ◽  
Jong-Bong Park ◽  
Soon-Gil Yoon
Keyword(s):  
Layer Thickness ◽  
Hafnium Oxide ◽  
Interfacial Layer ◽  
Gate Dielectric

Scalability of MOCVD-deposited Hafnium Oxide

2003 ◽  
Vol 765 ◽  
Author(s):  
S. Van Elshocht ◽  
R. Carter ◽  
M. Caymax ◽  
M. Claes ◽  
T. Conard ◽  
...  
Keyword(s):  
Hafnium Oxide ◽  
Interfacial Layer ◽  
Gate Dielectric ◽  
Deposition Process ◽  
Oxide Thickness ◽  
Process Conditions ◽  
Primary Concern ◽  
Gate Electrode ◽  
K Value ◽  
High K

AbstractBecause of aggressive downscaling to increase transistor performance, the physical thickness of the SiO2 gate dielectric is rapidly approaching the limit where it will only consist of a few atomic layers. As a consequence, this will result in very high leakage currents due to direct tunneling. To allow further scaling, materials with a k-value higher than SiO2 (“high-k materials”) are explored, such that the thickness of the dielectric can be increased without degrading performance.Based on our experimental results, we discuss the potential of MOCVD-deposited HfO2 to scale to (sub)-1-nm EOTs (Equivalent Oxide Thickness). A primary concern is the interfacial layer that is formed between the Si and the HfO2, during the MOCVD deposition process, for both H-passivated and SiO2-like starting surfaces. This interfacial layer will, because of its lower k-value, significantly contribute to the EOT and reduce the benefit of the high-k material. In addition, we have experienced serious issues integrating HfO2 with a polySi gate electrode at the top interface depending on the process conditions of polySi deposition and activation anneal used. Furthermore, we have determined, based on a thickness series, the k-value for HfO2 deposited at various temperatures and found that the k-value of the HfO2 depends upon the gate electrode deposited on top (polySi or TiN).Based on our observations, the combination of MOCVD HfO2 with a polySi gate electrode will not be able to scale below the 1-nm EOT marker. The use of a metal gate however, does show promise to scale down to very low EOT values.

Highly Reliable Thin Hafnium Oxide Gate Dielectric

1999 ◽  
Vol 592 ◽  
Author(s):  
Laegu Kang ◽  
Byoung-Hun Lee ◽  
Wen-Jie Qi ◽  
Yong-Joo Jeon ◽  
Renee Nieh ◽  
...  
Keyword(s):  
Hafnium Oxide ◽  
Interfacial Layer ◽  
Gate Dielectric ◽  
Frequency Dispersion ◽  
Deposition Process ◽  
Oxide Thickness ◽  
Mos Capacitors ◽  
Control Interface ◽  
High Resolution Tem ◽  
The One

ABSTRACTHfO2 is the one of the potential high-k dielectrics for replacing SiO2 as a gate dielectric. HfO2 is thermodynamically stable when in direct contact with Si and has a reasonable band gap (∼5.65eV). In this study, MOS capacitors (Pt/HfO2/Si) were fabricated by depositing HfO2 using reactive DC magnetron sputtering in the range of 33∼135Å followed by Pt deposition. During the HfO2 deposition, O2 flow was modulated to control interface quality and to suppress interfacial layer growing. By optimizing the HfO2 deposition process, equivalent oxide thickness (EOT) can be reduced down to ∼11.2 Å with the leakage current as low as 1X10−2 A/cm2 at +1.0V and negligible frequency dispersion. HfO2 films also show excellent breakdown characteristics and negligible hysteresis after high temperature annealing. From the high resolution TEM, there is a thin interfacial layer after annealing, suggesting a composite of Si-Hf-O with a dielectric constant of ≈ 2 X K SiO2.

Nitrogen (N2) Implantation to Suppress Growth of Interfacial Oxide in Mocvd Bst and Sputtered Bst Films

1999 ◽  
Vol 567 ◽  
Author(s):  
Renee Nieh ◽  
Wen-Jie Qi ◽  
Yongjoo Jeon ◽  
Byoung Hun Lee ◽  
Aaron Lucas ◽  
...  
Keyword(s):  
Photoelectron Spectroscopy ◽  
Interfacial Layer ◽  
Gate Dielectric ◽  
Nitrogen Concentration ◽  
Chemical Vapor ◽  
Future Generation ◽  
Oxide Thickness ◽  
Layer Growth ◽  
X Ray ◽  
Bst Films

ABSTRACTBa0.5Sr0.5TiO3 (BST) is one of the high-k candidates for replacing SiO2 as the gate dielectric in future generation devices. The biggest obstacle to scaling the equivalent oxide thickness (EOT) of BST is an interfacial layer, SixOy, which forms between BST and Si. Nitrogen (N2) implantation into the Si substrate has been proposed to reduce the growth of this interfacial layer. In this study, capacitors (Pt/BST/Si) were fabricated by depositing thin BST films (50Å) onto N2 implanted Si in order to evaluate the effects of implant dose and annealing conditions on EOT. It was found that N2 implantation reduced the EOT of RF magnetron sputtered and Metal Oxide Chemical Vapor Deposition (MOCVD) BST films by ∼20% and ∼33%, respectively. For sputtered BST, an implant dose of 1×1014cm−;2 provided sufficient nitrogen concentration without residual implant damage after annealing. X-ray photoelectron spectroscopy data confirmed that the reduction in EOT is due to a reduction in the interfacial layer growth. X-ray diffraction spectra revealed typical polycrystalline structure with (111) and (200) preferential orientations for both films. Leakage for these 50Å BST films is on the order of 10−8 to 10−5 A/cm2—lower than oxynitrides with comparable EOTs.

Effect of inner oxygen on the interfacial layer formation for HfO2 gate dielectric

2007 ◽  
Vol 42 (17) ◽  
pp. 7343-7347 ◽  
Author(s):  
Ran Jiang ◽  
E. Q. Xie ◽  
Z. F. Wang
Keyword(s):  
Interfacial Layer ◽  
Gate Dielectric ◽  
Layer Formation

Electrical characteristics of highly reliable ultrathin hafnium oxide gate dielectric

2000 ◽  
Vol 21 (4) ◽  
pp. 181-183 ◽  
Author(s):  
Laegu Kang ◽  
Byoung Hun Lee ◽  
Wen-Jie Qi ◽  
Yongjoo Jeon ◽  
R. Nieh ◽  
...  
Keyword(s):  
Hafnium Oxide ◽  
Gate Dielectric ◽  
Electrical Characteristics

scholarly journals Impact of interfacial layer thickness on gate stack-based DGTFET: an analog/RF prospective

2021 ◽  
Vol 1070 (1) ◽  
pp. 012081
Author(s):  
Vibhu Goyal ◽  
Shubham Tayal ◽  
Shweta Meena ◽  
Ravi Gupta
Keyword(s):  
Layer Thickness ◽  
Interfacial Layer ◽  
Gate Stack

Effect of High Temperature Forming Gas Annealing on Electrical Properties of 4H-SiC Lateral MOSFETs with Lanthanum Silicate and ALD SiO2 Gate Dielectric

2018 ◽  
Vol 924 ◽  
pp. 482-485
Author(s):  
Min Seok Kang ◽  
Kevin Lawless ◽  
Bong Mook Lee ◽  
Veena Misra
Keyword(s):  
Threshold Voltage ◽  
Interfacial Layer ◽  
Field Effect ◽  
Lanthanum Oxide ◽  
Gate Dielectric ◽  
High Mobility ◽  
High Threshold ◽  
Field Effect Mobility ◽  
The Impact ◽  
Lanthanum Silicate

We investigated the impact of an initial lanthanum oxide (La2O3) thickness and forming gas annealing (FGA) conditions on the MOSFET performance. The FGA has been shown to dramatically improve the threshold voltage (VT) stability of 4H-SiC MOSFETs. The FGA process leads to low VTshift and high field effect mobility due to reduction of the interface states density as well as traps by passivating the dangling bonds and active traps in the Lanthanum Silicate dielectrics. By optimizing the La2O3interfacial layer thickness and FGA condition, SiC MOSFETs with high threshold voltage and high mobility while maintaining minimal VTshift are realized.

Impact of GeOx interfacial layer thickness on Al2O3/Ge MOS interface properties

2011 ◽  
Vol 88 (7) ◽  
pp. 1533-1536 ◽  
Author(s):  
R. Zhang ◽  
T. Iwasaki ◽  
N. Taoka ◽  
M. Takenaka ◽  
S. Takagi
Keyword(s):  
Layer Thickness ◽  
Interfacial Layer ◽  
Interface Properties
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