Nano-Scale Simulation of Platinum Particle Dissolution, Re-Deposition, and Transport

Encapsulation is a process of enclosing the substances within an inert material which protects from environment as well as control drug release. Recently, two type of encapsulation has been performed in several research. Nanoencapsulation is the coating of various substances within another material at sizes on the nano scale. Microencapsulation is similar to nanoencapsulation aside from it involving larger particles and having been done for a greater period of time than nanoencapsulation. Encapsulation is a new technology that has wide applications in pharmaceutical industries, agrochemical, food industries and cosmetics. In this review, the difference between micro and nano encapsulation has been explained. This article gives an overview of different methods and reason for encapsulation. The advantages and disadvantages of micro and nano encapsulation technology were also clearly mentioned in this paper.

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The effect of stochastic nano-scale surface roughness on microfluidic flow in computational microchannels

10.31274/etd-180810-2412 ◽

2012 ◽

Cited By ~ 1

Author(s):

Robert Jaeger

Keyword(s):

Surface Roughness ◽

Nano Scale ◽

Microfluidic Flow ◽

Scale Surface

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Nanoscale Capacitance and Capacitance-Voltage Curves for Advanced Characterization of Electrical Properties of Si and GaN Structures Using Scanning Microwave Impedance Microscopy

ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2016p0449 ◽

2016 ◽

Author(s):

Stuart Friedman ◽

Oskar Amster ◽

Yongliang Yang ◽

Fred Stanke

Keyword(s):

Process Development ◽

Advanced Characterization ◽

Electrical Measurement ◽

Depletion Layer ◽

Doped Semiconductors ◽

Force Microscopy ◽

Nano Scale ◽

Capacitance Voltage ◽

Systematic Response ◽

Lock In

Abstract The use of Atomic Force Microscopy (AFM) electrical measurement modes is a critical tool for the study of semiconductor devices and process development. A relatively new electrical mode, scanning microwave impedance microscopy (sMIM), measures a material’s change in permittivity and conductivity at the scale of an AFM probe tip [1]. sMIM provides the real and imaginary impedance (Re(Z) and Im(Z)) of the probe-sample interface. By measuring the reflected microwave signal as a sample of interest is imaged with an AFM, we can in parallel capture the variations in permittivity and conductivity and, for doped semiconductors, variations in the depletion-layer geometry. An existing technique for characterizing doped semiconductors, scanning capacitance microscopy, modulates the tip-sample bias and detects the tip-sample capacitance with a lock-in amplifier. A previous study compares sMIM to SCM and highlights the additional capabilities of sMIM [2], including examples of nano-scale capacitance-voltage curves. In this paper we focus on the detailed mechanisms and capabilities of the nano-scale C-V curves and the ability to extract semiconductor properties from them. This study includes analytical and finite element modeling of tip bias dependent depletion-layer geometry and impedance. These are compared to experimental results on reference samples for both doped Si and GaN doped staircases to validate the systematic response of the sMIM-C (capacitive) channel to the doping concentration.

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A Case Study of Defects Due to Process-Design Interaction in Nano Scale Technology

ISTFA 2007: Conference Proceedings from the 33rd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2007p0172 ◽

2007 ◽

Author(s):

Hung-Sung Lin ◽

Ying-Chin Hou ◽

Juimei Fu ◽

Mong-Sheng Wu ◽

Vincent Huang ◽

...

Keyword(s):

Liquid Crystal ◽

Circuit Design ◽

Process Design ◽

Integrated Circuit ◽

Photon Emission ◽

Integrated Circuit Design ◽

Nano Scale ◽

Leakage Path ◽

Related Defect

Abstract The difficulties in identifying the precise defect location and real leakage path is increasing as the integrated circuit design and process have become more and more complicated in nano scale technology node. Most of the defects causing chip leakage are detectable with only one of the FA (Failure Analysis) tools such as LCD (Liquid Crystal Detection) or PEM (Photon Emission Microscope). However, due to marginality of process-design interaction some defects are often not detectable with only one FA tool [1][2]. This paper present an example of an abnormal power consumption process-design interaction related defect which could only be detected with more advanced FA tools.

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