(Invited) Record-Performance In(Ga)As MOSFETS Targeting ITRS High-Performance and Low-Power Logic

2015 ◽  
Vol 66 (4) ◽  
pp. 135-140 ◽  
Author(s):  
M. J. Rodwell ◽  
C.-Y. Huang ◽  
S. Lee ◽  
V. Chobpattana ◽  
B. Thibeault ◽  
...  
Keyword(s):  
Low Power ◽  
High Performance ◽  
Low Power Logic

CHALLENGE OF MTJ-BASED NONVOLATILE LOGIC-IN-MEMORY ARCHITECTURE FOR DARK-SILICON LOGIC LSI

SPIN ◽  
2013 ◽  
Vol 03 (04) ◽  
pp. 1340014 ◽  
Author(s):  
TAKAHIRO HANYU
Keyword(s):  
Low Power ◽  
Performance Improvement ◽  
Tunnel Junction ◽  
High Performance ◽  
Magnetic Tunnel Junction ◽  
Memory Architecture ◽  
Dark Silicon ◽  
Ultra Low Power ◽  
Power Wall ◽  
Low Power Logic

This paper presents an architecture-level approach, called nonvolatile logic-in-memory (NV-LIM) architecture, to solving performance-wall and power-wall problems in the present CMOS-only-based logic-LSI (Large-Scaled Integration) processors. The use of magnetic tunnel junction devices combined with a CMOS-gate style makes it possible to achieve a high-performance and ultra-low-power logic LSI. Some concrete examples using the proposed method allow you to achieve the desired performance improvement compared to a corresponding CMOS-only-based realization.

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