scholarly journals Negative Capacitance Tunnel Field Effect Transistor: A Novel Device with Low Subthreshold Swing and High on Current

2014 ◽  
Vol 58 (16) ◽  
pp. 1-8 ◽  
Author(s):  
N. Chowdhury ◽  
S. M. F. Azad ◽  
Q. D. M. Khosru
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Subthreshold Swing ◽  
Negative Capacitance ◽  
Novel Device ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor

Gate-controlled MoTe2 homojunction for sub-thermionic subthreshold swing tunnel field-effect transistor

Nano Today ◽  
2021 ◽  
Vol 40 ◽  
pp. 101263
Author(s):  
Ngoc Thanh Duong ◽  
Chulho Park ◽  
Duc Hieu Nguyen ◽  
Phuong Huyen Nguyen ◽  
Thi Uyen Tran ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Subthreshold Swing ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor

scholarly journals Impact of Band-Tails on the Subthreshold Swing of III-V Tunnel Field-Effect Transistor

2017 ◽  
Vol 38 (12) ◽  
pp. 1661-1664 ◽  
Author(s):  
E. Memisevic ◽  
E. Lind ◽  
M. Hellenbrand ◽  
J. Svensson ◽  
L.-E. Wernersson
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Subthreshold Swing ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Band Tails

scholarly journals Performance Analysis of Vertically Stacked Nanosheet Tunnel Field Effect Transistor with Ideal Subthreshold Swing

2021 ◽  
Author(s):  
Garima Jain ◽  
Ravinder Singh Sawhney ◽  
Ravinder Kumar ◽  
Amit Saini
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Subthreshold Swing ◽  
Short Channel ◽  
Tunneling Mechanism ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor

Abstract In this paper, a novel vertically stacked silicon Nanosheet Tunnel Field Effect Transistor (NS-TFET) device scaled to a gate length of 12nm with Contact poly pitch (CPP) of 48nm is simulated. NS-TFET device is investigated for its electrostatics characteristics using technology computer-aided design (TCAD) simulator. The inter-band tunneling mechanism with a P-I-N layout has been incorporated in the stacked nanosheet devices. The asymmetric design technique for doping has been used for optimum results. NS-TFET provides a low leakage current of order10-16 A, an excellent subthreshold swing (SW) of 23mv/decade, and negligible drain induced barrier lowering (DIBL) having a value of 10.5 mv/V. The notable ON to OFF current ratio of the order of 1011 has been achieved. The device exhibits a high transconductance of 3.022x10-5 S at the gate to source voltage of 1V. NS-TFET shows tremendous improvement in short channel effects (SCE) and is a good option for advanced technologies.

Structural Modification of Doped Tunnel Field Effect Transistor for Enhanced Conduction Current and Lower Subthreshold Swing

2019 ◽  
Vol 14 (11) ◽  
pp. 1539-1547
Author(s):  
Deepak Soni ◽  
Amit Kumar Behera ◽  
Dheeraj Sharma ◽  
Dip Prakash Samajdar ◽  
Dharmendra Singh Yadav
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Metal Layer ◽  
Source Region ◽  
Subthreshold Swing ◽  
Electrical Characteristics ◽  
Gate Electrode ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Rf Performance

The material solubility in the source region and abrupt source/channel junction profile are the major concern which is responsible for the improvement of the electrical characteristics of conventional physical doped tunnel field effect transistor (PD-TFET). For this, an additional negatively polarised electrode is mounted in P+ (source) – N (channel) – N+ (drain) structure over the source region to overcome material solubility. This improves the electrical characteristics of the device. Along with this, we have implanted a low workfunction metal layer (ML) in the oxide layer under the gate electrode for creating more abruptness at the junction to improve the subthreshold swing (SS) of the device. Thus, the proposed concept improves the DC/RF performance of the doped TFET device. Further to this, the optimization of metal layer workfunction and misalignment of metal layer in TFET have been performed to get optimum device characteristics. In addition to this, for the suppression of ambipolar behaviour, gate electrode is shorted from the drain side. Due to short length of gate electrode tunneling barrier width at the drain/channel junction increases, hence the tunneling probability decreases which reduces the ambipolar current to parasitic current. Shortening of gate electrode also improves the RF performance.

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