Optimized Contact Engineering to Maximize Cell Current in NAND Flash Memory Technology

2013 ◽  
Vol 58 (5) ◽  
pp. 103-108
Author(s):  
J. H. Yoon ◽  
H.-S. Kim ◽  
Y. S. Kim ◽  
J. K. Lee ◽  
E. S. Han ◽  
...  
Keyword(s):  
Flash Memory ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Cell Current ◽  
Contact Engineering

Variation of Threshold Voltage and ON-Cell Current Caused by Cell Gate Length Fluctuation in Virtual Source/Drain NAND Flash Memory

2012 ◽  
Vol 51 ◽  
pp. 074301 ◽  
Author(s):  
Wandong Kim ◽  
Yoon Kim ◽  
Se Hwan Park ◽  
Joo Yun Seo ◽  
Do Bin Kim ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Flash Memory ◽  
Gate Length ◽  
Nand Flash ◽  
Virtual Source ◽  
Nand Flash Memory ◽  
Cell Current

Variation of Threshold Voltage and ON-Cell Current Caused by Cell Gate Length Fluctuation in Virtual Source/Drain NAND Flash Memory

2012 ◽  
Vol 51 (7R) ◽  
pp. 074301 ◽  
Author(s):  
Wandong Kim ◽  
Yoon Kim ◽  
Se Hwan Park ◽  
Joo Yun Seo ◽  
Do Bin Kim ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Flash Memory ◽  
Gate Length ◽  
Nand Flash ◽  
Virtual Source ◽  
Nand Flash Memory ◽  
Cell Current

A cell current compensation scheme for 3D NAND FLASH memory

2015 ◽  
Author(s):  
SungWook Choi ◽  
KyuTae Park ◽  
Marco Passerini ◽  
HeeJoung Park ◽  
DoYoung Kim ◽  
...  
Keyword(s):  
Flash Memory ◽  
Nand Flash ◽  
Compensation Scheme ◽  
Nand Flash Memory ◽  
Current Compensation ◽  
Cell Current ◽  
A Cell

Novel Three Dimensional (3D) NAND Flash Memory Array Having Tied Bit-line and Ground Select Transistor (TiGer)

2012 ◽  
Vol E95.C (5) ◽  
pp. 837-841 ◽  
Author(s):  
Se Hwan PARK ◽  
Yoon KIM ◽  
Wandong KIM ◽  
Joo Yun SEO ◽  
Hyungjin KIM ◽  
...  
Keyword(s):  
Flash Memory ◽  
Three Dimensional ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Memory Array

scholarly journals Artificial Neural Network Assisted Error Correction for MLC NAND Flash Memory

Micromachines ◽  
2021 ◽  
Vol 12 (8) ◽  
pp. 879
Author(s):  
Ruiquan He ◽  
Haihua Hu ◽  
Chunru Xiong ◽  
Guojun Han
Keyword(s):  
Neural Network ◽  
Error Correction ◽  
Error Detection ◽  
Flash Memory ◽  
Nand Flash ◽  
Data Reliability ◽  
Nand Flash Memory ◽  
Process Technology ◽  
Noise Mitigation ◽  
Memory Channel

The multilevel per cell technology and continued scaling down process technology significantly improves the storage density of NAND flash memory but also brings about a challenge in that data reliability degrades due to the serious noise. To ensure the data reliability, many noise mitigation technologies have been proposed. However, they only mitigate one of the noises of the NAND flash memory channel. In this paper, we consider all the main noises and present a novel neural network-assisted error correction (ANNAEC) scheme to increase the reliability of multi-level cell (MLC) NAND flash memory. To avoid using retention time as an input parameter of the neural network, we propose a relative log-likelihood ratio (LLR) to estimate the actual LLR. Then, we transform the bit detection into a clustering problem and propose to employ a neural network to learn the error characteristics of the NAND flash memory channel. Therefore, the trained neural network has optimized performances of bit error detection. Simulation results show that our proposed scheme can significantly improve the performance of the bit error detection and increase the endurance of NAND flash memory.

scholarly journals Investigation of Re-program Scheme in Charge Trap Based 3D NAND Flash Memory

2021 ◽  
pp. 1-1
Author(s):  
Ting Cheng ◽  
Jianquan Jia ◽  
Lei Jin ◽  
Xinlei Jia ◽  
Shiyu Xia ◽  
...  
Keyword(s):  
Flash Memory ◽  
Program Scheme ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Charge Trap
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