A highly configurable cache architecture for embedded systems

Chuanjun Zhang; Frank Vahid; Walid Najjar

doi:10.1145/871656.859635

A highly configurable cache architecture for embedded systems

ACM SIGARCH Computer Architecture News ◽

10.1145/871656.859635 ◽

2003 ◽

Vol 31 (2) ◽

pp. 136-146 ◽

Cited By ~ 15

Author(s):

Chuanjun Zhang ◽

Frank Vahid ◽

Walid Najjar

Keyword(s):

Embedded Systems ◽

Cache Architecture ◽

Configurable Cache

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A highly configurable cache architecture for embedded systems

30th Annual International Symposium on Computer Architecture, 2003. Proceedings. ◽

10.1145/859618.859635 ◽

2003 ◽

Cited By ~ 141

Author(s):

Chuanjun Zhang ◽

Frank Vahid ◽

Walid Najjar

Keyword(s):

Embedded Systems ◽

Cache Architecture ◽

Configurable Cache

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A Capacity Co-allocation Configurable Cache for Low Power Embedded Systems

2006 International Conference on Computer Design ◽

10.1109/iccd.2006.4380848 ◽

2006 ◽

Cited By ~ 2

Author(s):

Chuanjun Zhang

Keyword(s):

Embedded Systems ◽

Low Power ◽

Configurable Cache

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A highly configurable cache for low energy embedded systems

ACM Transactions on Embedded Computing Systems ◽

10.1145/1067915.1067921 ◽

2005 ◽

Vol 4 (2) ◽

pp. 363-387 ◽

Cited By ~ 60

Author(s):

Chuanjun Zhang ◽

Frank Vahid ◽

Walid Najjar

Keyword(s):

Embedded Systems ◽

Low Energy ◽

Configurable Cache

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Realizing Closed-Loop, Online Tuning and Control for Configurable-Cache Embedded Systems: Progress and Challenges

2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) ◽

10.1109/isvlsi.2018.00136 ◽

2018 ◽

Author(s):

Islam Badreldin ◽

Ann Gordon-Ross ◽

Tosiron Adegbija ◽

Mohamad Hammam Alsafrjalaniz

Keyword(s):

Embedded Systems ◽

Closed Loop ◽

And Control ◽

Online Tuning ◽

Configurable Cache

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SLAM: High Performance and Energy Efficient Hybrid Last Level Cache Architecture for Multicore Embedded Systems

2019 IEEE International Conference on Embedded Software and Systems (ICESS) ◽

10.1109/icess.2019.8782441 ◽

2019 ◽

Author(s):

Swapnil Bhosale ◽

Sudeep Pasricha

Keyword(s):

Embedded Systems ◽

Energy Efficient ◽

High Performance ◽

Cache Architecture

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Time-sensitivity-aware shared cache architecture for multi-core embedded systems

The Journal of Supercomputing ◽

10.1007/s11227-019-02891-w ◽

2019 ◽

Vol 75 (10) ◽

pp. 6746-6776

Author(s):

Myoungjun Lee ◽

Soontae Kim

Keyword(s):

Embedded Systems ◽

Shared Cache ◽

Cache Architecture ◽

Time Sensitivity

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Online First Fit Algorithm for modeling the problem of configurable cache architecture

ICM 2011 Proceeding ◽

10.1109/icm.2011.6177402 ◽

2011 ◽

Author(s):

Asmaa Bengueddach ◽

Smail Niar ◽

Bouziane Beldjilali

Keyword(s):

Cache Architecture ◽

Configurable Cache

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A fine-grained configurable cache architecture for soft processors

2015 18th CSI International Symposium on Computer Architecture and Digital Systems (CADS) ◽

10.1109/cads.2015.7377783 ◽

2015 ◽

Cited By ~ 2

Author(s):

Mehrdad Biglari ◽

Kamyar Mirzazad Barijough ◽

Maziar Goudarzi ◽

Behnaz Pourmohseni

Keyword(s):

Fine Grained ◽

Cache Architecture ◽

Configurable Cache

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A single cycle accessible two-level cache architecture for reducing the energy consumption of embedded systems

2008 International SoC Design Conference ◽

10.1109/socdc.2008.4815604 ◽

2008 ◽

Author(s):

Seiichiro Yamaguchi ◽

Tohru Ishihara ◽

Hiroto Yasuura

Keyword(s):

Energy Consumption ◽

Embedded Systems ◽

Single Cycle ◽

Cache Architecture

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A self-tuning cache architecture for embedded systems

ACM Transactions on Embedded Computing Systems ◽

10.1145/993396.993405 ◽

2004 ◽

Vol 3 (2) ◽

pp. 407-425 ◽

Cited By ~ 66

Author(s):

Chuanjun Zhang ◽

Frank Vahid ◽

Roman Lysecky

Keyword(s):

Embedded Systems ◽

Cache Architecture ◽

Self Tuning

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