scholarly journals Slowing down sorting networks to obtain faster sorting algorithms

1987 ◽  
Vol 34 (1) ◽  
pp. 200-208 ◽  
Author(s):  
Richard Cole
2017 ◽  
Author(s):  
Thorsten Ehlers

In this thesis, we consider the parallelisation and application of SAT and CP solvers. In the first chapter, we consider SAT, the decision problem of propositional logic. We discuss details of the implementations of SAT solvers, and show how to improve upon existing sequential solvers. Furthermore, we discuss the parallelisation of these solvers with a focus on the communication of intermediate results within a parallel solver. The second chapter is concerned with Contraint Programing (CP) with learning. Contrary to classical Constraint Programming techniques, this incorporates learning mechanisms as they are used in the field of SAT solving. We present results from parallelising CHUFFED, a learning CP solver. In the final chapter, we discuss Sorting Networks, which are data oblivious sorting algorithms. Their independence of the input data lends them to parallel implementation. We consider the question how many parallel sorting steps are needed to sort some inputs, and present both lower and upper bounds for several cases.


2017 ◽  
Author(s):  
Thorsten Ehlers

In this thesis, we consider the parallelisation and application of SAT and CP solvers. In the first chapter, we consider SAT, the decision problem of propositional logic. We discuss details of the implementations of SAT solvers, and show how to improve upon existing sequential solvers. Furthermore, we discuss the parallelisation of these solvers with a focus on the communication of intermediate results within a parallel solver. The second chapter is concerned with Contraint Programing (CP) with learning. Contrary to classical Constraint Programming techniques, this incorporates learning mechanisms as they are used in the field of SAT solving. We present results from parallelising CHUFFED, a learning CP solver. In the final chapter, we discuss Sorting Networks, which are data oblivious sorting algorithms. Their independence of the input data lends them to parallel implementation. We consider the question how many parallel sorting steps are needed to sort some inputs, and present both lower and upper bounds for several cases.


2011 ◽  
Vol 2011 ◽  
pp. 1-12 ◽  
Author(s):  
Jorge Ortiz ◽  
David Andrews

Popular sorting algorithms do not translate well into hardware implementations. Instead, hardware-based solutions like sorting networks, systolic sorters, and linear sorters exploit parallelism to increase sorting efficiency. Linear sorters, built from identical nodes with simple control, have less area and latency than sorting networks, but they are limited in their throughput. We present a system composed of multiple linear sorters acting in parallel to increase overall throughput. Interleaving is used to increase bandwidth and allow sorting of multiple values per clock cycle, and the amount of interleaving and depth of the linear sorters can be adapted to suit specific applications. Contention for available linear sorters in the system is solved through the use of buffers that accumulate conflicting requests, dispatching them in bulk to reduce latency penalties. Implementation of this system into a field programmable gate array (FPGA) results in a speedup of 68 compared to a MicroBlaze processor running quicksort.


Energies ◽  
2018 ◽  
Vol 11 (9) ◽  
pp. 2394 ◽  
Author(s):  
Mattia Ricco ◽  
Laszlo Mathe ◽  
Eric Monmasson ◽  
Remus Teodorescu

In Modular Multilevel Converter (MMC) applications, the balancing of the capacitor voltages is one of the most important issues for achieving the proper behavior of the MMC. The Capacitor Voltage Balancing (CVB) control is usually based on classical sorting algorithms which consist of repetitive/recursive loops. This leads to an increase of the execution time when many Sub-Modules (SMs) are employed. When the execution time of the balancing is longer than the sampling period, the proper operation of the MMC cannot be ensured. Moreover, due to their inherent sequential operation, sorting algorithms are suitable for software implementation (microcontrollers or DSPs), but they are not appropriate for a hardware implementation. Instead, in this paper, Sorting Networks (SNs) are proposed due to their convenience for implementation in FPGA devices. The advantages and the main challenges of the Bitonic SN in MMC applications are discussed and different FPGA implementations are presented. Simulation results are provided in normal and faulty conditions. Moreover, a comparison with the widely used bubble sorting algorithm and max/min approach is made in terms of execution time and performance. Finally, hardware-in-the-loop results are shown to prove the effectiveness of the implemented SN.


2019 ◽  
Vol 29 (04) ◽  
pp. 1950015
Author(s):  
Avah Banerjee ◽  
Dana Richards

Sorting networks are a class of parallel oblivious sorting algorithms. Not only do they have interesting theoretical properties but they can be fabricated. A sorting network is a sequence of parallel compare-exchange operations using comparators which are grouped into stages. This underlying graph defines the topology of the network. The majority of results on sorting networks concern the unrestricted case where the underlying graph is the complete graph. Prior results are also known for paths, hypercubes, and meshes. In this paper we introduce a sorting network whose underlying topology is a tree and formalize the concept of sorting networks on a restricted graph topology by introducing a new parameter for graphs called its sorting number. The main result of the paper is a description of an [Formula: see text] depth sorting network on a tree with maximum degree [Formula: see text].


2016 ◽  
Vol 29 (3) ◽  
pp. 559-579 ◽  
Author(s):  
Michael Codish ◽  
Luís Cruz-Filipe ◽  
Markus Nebel ◽  
Peter Schneider-Kamp

2018 ◽  
Vol 6 (1) ◽  
pp. 133-153
Author(s):  
Toufan Aldian Syah

Banking industry has a very important role in economic development in a country. Indonesia, which is the largest Muslim country in the world, certainly has the prospect of the development of Sharia Banking Industry is very good in the future. However, the development of Sharia Bank has been slowing down in recent years and the profitability of sharia comercial banking is still below the ideal value. This study aims to determine the internal factors and external factors that affect the profitability of Sharia Bank in the year of January 2012 until August 2017. The variables used in this study are ROA, Inflation, NPF, and BOPO. The data used is aggregate data of all Sharia Commercial Banks recorded at Bank Indonesia. Measurement of Statistic Description, F-Test, T-Test, Correlation Coefficient, Coefficient of Determination and Multiple Linear Regression using IBM SPSS 21 software. The results showed that significant negative effect of BI rate, NPF and BOPO was found, while Inflation variable showed negative but not significant. Overall, the above variables affect the ROA of 87.7%, while 12.3% is likely to be influenced by other factors.


2019 ◽  
Vol 19 (5) ◽  
pp. 368-381 ◽  
Author(s):  
Linh N.K. Tran ◽  
Ganessan Kichenadasse ◽  
Pamela J. Sykes

Prostate cancer (PCa) is the most frequent cancer in men. The evolution from local PCa to castration-resistant PCa, an end-stage of disease, is often associated with changes in genes such as p53, androgen receptor, PTEN, and ETS gene fusion products. Evidence is accumulating that repurposing of metformin (MET) and valproic acid (VPA) either when used alone, or in combination, with another therapy, could potentially play a role in slowing down PCa progression. This review provides an overview of the application of MET and VPA, both alone and in combination with other drugs for PCa treatment, correlates the responses to these drugs with common molecular changes in PCa, and then describes the potential for combined MET and VPA as a systemic therapy for prostate cancer, based on potential interacting mechanisms.


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