Achieving independence in logarithmic number of rounds

1987 ◽  
Author(s):  
Benny Chor ◽  
Michael O. Rabin
Keyword(s):  
Logarithmic Number

scholarly journals Hybrid Floating Point/Logarithmic Number System Processor

2020 ◽  
Vol 932 ◽  
pp. 012059
Author(s):  
C Y Sheng ◽  
R C Ismail ◽  
S Z M Naziri ◽  
M N M Isa ◽  
S A Z Murad ◽  
...  
Keyword(s):  
Number System ◽  
Floating Point ◽  
Logarithmic Number System ◽  
Logarithmic Number

Semi-logarithmic number systems

1998 ◽  
Vol 47 (2) ◽  
pp. 145-151 ◽  
Author(s):  
J.-M. Muller ◽  
A. Scherbyna ◽  
A. Tisserand
Keyword(s):  
Number Systems ◽  
Logarithmic Number

Implementing the Residue Logarithmic Number System Using Interpolation and Cotransformation

2020 ◽  
Vol 69 (12) ◽  
pp. 1719-1732 ◽  
Author(s):  
Mark G. Arnold ◽  
Vassilis Paliouras ◽  
Ioannis Kouretas
Keyword(s):  
Number System ◽  
Logarithmic Number System ◽  
Logarithmic Number

scholarly journals RISC Conversions for LNS Arithmetic in Embedded Systems

Mathematics ◽  
2020 ◽  
Vol 8 (8) ◽  
pp. 1208 ◽  
Author(s):  
Peter Drahoš ◽  
Michal Kocúr ◽  
Oto Haffner ◽  
Erik Kučera ◽  
Alena Kozáková
Keyword(s):  
Embedded Systems ◽  
Number System ◽  
Real Time Control ◽  
Gate Arrays ◽  
Time Control ◽  
Camera Systems ◽  
Control Units ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Logarithmic Number

The paper presents an original methodology for the implementation of the Logarithmic Number System (LNS) arithmetic, which uses Reduced Instruction Set Computing (RISC). The core of the proposed method is a newly developed algorithm for conversion between LNS and the floating point (FLP) representations named “looping in sectors”, which brings about reduced memory consumption without a loss of accuracy. The resulting effective RISC conversions use only elementary computer operations without the need to employ multiplication, division, or other functions. Verification of the new concept and related developed algorithms for conversion between the LNS and the FLP representations was realized on Field Programmable Gate Arrays (FPGA), and the conversion accuracy was evaluated via simulation. Using the proposed method, a maximum relative conversion error of less than ±0.001% was achieved with a 22-ns delay and a total of 50 slices of FPGA consumed including memory cells. Promising applications of the proposed method are in embedded systems that are expanding into increasingly demanding applications, such as camera systems, lidars and 2D/3D image processing, neural networks, car control units, autonomous control systems that require more computing power, etc. In embedded systems for real-time control, the developed conversion algorithm can appear in two forms: as RISC conversions or as a simple RISC-based logarithmic addition.

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