Some characteristics of sorting computing systems using random access storage devices

1963 ◽  
Vol 6 (5) ◽  
pp. 248-255 ◽  
Author(s):  
George U. Hubbard
Keyword(s):  
Random Access ◽  
Computing Systems ◽  
Storage Devices

scholarly journals Implications of NVM Based Storage on Memory Subsystem Management

2020 ◽  
Vol 10 (3) ◽  
pp. 999
Author(s):  
Hyokyung Bahn ◽  
Kyungwoon Cho
Keyword(s):  
Random Access ◽  
Disk Drive ◽  
Main Memory ◽  
Memory Storage ◽  
Storage Device ◽  
Storage Devices ◽  
Large Memory ◽  
Memory Subsystems ◽  
Non Volatile Memory ◽  
Management Techniques

Recently, non-volatile memory (NVM) has advanced as a fast storage medium, and legacy memory subsystems optimized for DRAM (dynamic random access memory) and HDD (hard disk drive) hierarchies need to be revisited. In this article, we explore the memory subsystems that use NVM as an underlying storage device and discuss the challenges and implications of such systems. As storage performance becomes close to DRAM performance, existing memory configurations and I/O (input/output) mechanisms should be reassessed. This article explores the performance of systems with NVM based storage emulated by the RAMDisk under various configurations. Through our measurement study, we make the following findings. (1) We can decrease the main memory size without performance penalties when NVM storage is adopted instead of HDD. (2) For buffer caching to be effective, judicious management techniques like admission control are necessary. (3) Prefetching is not effective in NVM storage. (4) The effect of synchronous I/O and direct I/O in NVM storage is less significant than that in HDD storage. (5) Performance degradation due to the contention of multi-threads is less severe in NVM based storage than in HDD. Based on these observations, we discuss a new PC configuration consisting of small memory and fast storage in comparison with a traditional PC consisting of large memory and slow storage. We show that this new memory-storage configuration can be an alternative solution for ever-growing memory demands and the limited density of DRAM memory. We anticipate that our results will provide directions in system software development in the presence of ever-faster storage devices.

scholarly journals A Durable Hybrid RAM Disk with a Rapid Resilience for Sustainable IoT Devices

Sensors ◽  
2020 ◽  
Vol 20 (8) ◽  
pp. 2159 ◽  
Author(s):  
Sung Hoon Baek ◽  
Ki-Woong Park
Keyword(s):  
Storage System ◽  
Random Access ◽  
Solid State Drive ◽  
Storage Devices ◽  
Disk Storage ◽  
Block Level ◽  
Iot Platforms ◽  
Iot Devices ◽  
Time Required ◽  
Time Critical

Flash-based storage is considered to be a de facto storage module for sustainable Internet of things (IoT) platforms under a harsh environment due to its relatively fast speed and operational stability compared to disk storage. Although their performance is considerably faster than disk-based mechanical storage devices, the read and write latency still could not catch up with that of Random-access memory (RAM). Therefore, RAM could be used as storage devices or systems for time-critical IoT applications. Despite such advantages of RAM, a RAM-based storage system has limitations in its use for sustainable IoT devices due to its nature of volatile storage. As a remedy to this problem, this paper presents a durable hybrid RAM disk enhanced with a new read interface. The proposed durable hybrid RAM disk is designed for sustainable IoT devices that require not only high read/write performance but also data durability. It includes two performance improvement schemes: rapid resilience with a fast initialization and direct byte read (DBR). The rapid resilience with a fast initialization shortens the long booting time required to initialize the durable hybrid RAM disk. The new read interface, DBR, enables the durable hybrid RAM disk to bypass the disk cache, which is an overhead in RAM-based storages. DBR performs byte–range I/O, whereas direct I/O requires block-range I/O; therefore, it provides a more efficient interface than direct I/O. The presented schemes and device were implemented in the Linux kernel. Experimental evaluations were performed using various benchmarks at the block level till the file level. In workloads where reads and writes were mixed, the durable hybrid RAM disk showed 15 times better performance than that of Solid-state drive (SSD) itself.

Advances in RRAM Technology: Identifying and Mitigating Roadblocks

2016 ◽  
Vol 25 (01n02) ◽  
pp. 1640006 ◽  
Author(s):  
D. Veksler ◽  
G. Bersuker
Keyword(s):  
Material Properties ◽  
Random Access ◽  
Random Access Memory ◽  
Resistive Random Access Memory ◽  
Operating Speed ◽  
Physical Processes ◽  
Access Memory ◽  
Computing Systems ◽  
Operation Conditions ◽  
Power Operation

Superior scalability, endurance, low power operation, retention, and operating speed of filamentary crystalline HfOx-based resistive random access memory (RRAM) makes this technology promising for implementation in exascale neuromorphic computing systems. Challenges, roadblocks for the implementation, and possible resolutions are discussed. Technological solutions to overcome RRAM variability (both device-to-device and cycle-to-cycle) and read instability are discussed. Major material properties and operation conditions controlling performance of the crystalline HfOx-based RRAM devices are linked to physical processes determining RRAM characteristics.

Reducing the stochasticity of crystal nucleation to enable subnanosecond memory writing

Science ◽  
2017 ◽  
Vol 358 (6369) ◽  
pp. 1423-1427 ◽  
Author(s):  
Feng Rao ◽  
Keyuan Ding ◽  
Yuxing Zhou ◽  
Yonghui Zheng ◽  
Mengjiao Xia ◽  
...  
Keyword(s):  
High Speed ◽  
Amorphous State ◽  
Random Access ◽  
Crystal Nucleation ◽  
Antimony Telluride ◽  
Computing Systems ◽  
Operation Speed ◽  
Speed Up ◽  
Germanium Antimony Telluride ◽  
Working Efficiency

Operation speed is a key challenge in phase-change random-access memory (PCRAM) technology, especially for achieving subnanosecond high-speed cache memory. Commercialized PCRAM products are limited by the tens of nanoseconds writing speed, originating from the stochastic crystal nucleation during the crystallization of amorphous germanium antimony telluride(Ge2Sb2Te5). Here, we demonstrate an alloying strategy to speed up the crystallization kinetics. The scandium antimony telluride (Sc0.2Sb2Te3) compound that we designed allows a writing speed of only 700 picoseconds without preprogramming in a large conventional PCRAM device. This ultrafast crystallization stems from the reduced stochasticity of nucleation through geometrically matched and robust scandium telluride (ScTe) chemical bonds that stabilize crystal precursors in the amorphous state. Controlling nucleation through alloy design paves the way for the development of cache-type PCRAM technology to boost the working efficiency of computing systems.

Nanoscale Energy Transport in Information Technology Research With an Application to High-Density Data Storage Devices and Systems

2002 ◽  
Author(s):  
Mehdi Asheghi ◽  
Yizhang Yang ◽  
Sadegh M. Sadeghipour ◽  
James A. Bain ◽  
Katayun Barmak ◽  
...  
Keyword(s):  
Information Technology ◽  
Data Storage ◽  
Energy Transport ◽  
Random Access ◽  
Thermal Design ◽  
Optical Data ◽  
Thermally Induced ◽  
Storage Devices ◽  
Superparamagnetic Limit ◽  
It Revolution

By all measures, the data storage industry is one of the most important components of the Information Technology (IT) revolution. In recent years, many of the emerging technologies rely heavily on energy transport at extremely short time and length scales as a mean to overcome the superparamagnetic limit - a serious impediment to future advancement of storage technology. Additionally, thermally induced failure and reliability issues at the nanoscale are becoming increasingly important due to rapid device miniaturization in data storage applications. Further advances in high-technology data storage systems will be difficult, if not impossible, without rigorous treatment of nanoscale energy transport. This manuscript reviews the thermal design issues and challenges in thermally assisted magnetic disk recording, thermally assisted scanned probe recording, phase change optical data recording, magnetoresistive random access memory (MRAM) and giant magnetoresistive (GMR) heads. Relevant thermally induced failures in GMR heads, write coil, interconnects and MRAM will be discussed as well.

Spin Valves in Microelectronics. Review

2021 ◽  
Vol 26 (1) ◽  
pp. 7-29
Author(s):  
Iu.A. Iusipova ◽  
◽  
A.I. Popov ◽  
Keyword(s):  
Giant Magnetoresistance ◽  
Spin Valve ◽  
Random Access ◽  
Cmos Technology ◽  
Work Conditions ◽  
Spin Transfer ◽  
Boolean Logic ◽  
Spin Valves ◽  
Computing Systems ◽  
Technology Scaling

The base element of micromagnetic devices are the layered spin-valve structures. Small sizes, compatibility with the CMOS technology, scaling ability and various work conditions make the spin-valve structures a universal component of modern microelectronics. The purpose of present work is the analysis, systematization and generalization of the data of the work theoretical bases, experimental data and the application of spin valves. In the review, the hard disc drives, random-access magnetoresistive memory, the spin-transfer nano-oscillators, the magnetic biosensors, as well as various computing systems, operating on the principles of stochastic and deterministic logic, have been considered. The key theoretical works devoted to giant magnetoresistance and spin transfer have been used. The data on various types of the hard-disc readheads have been systematized, their architecture and parameters have been compared, and it has been shown how modern scientific research of nanomagnetic phenomena accelerates the growth rate of the recording density. The analysis of modern research devoted to magnetoresistive random access memory has been carried out. The problems of energy efficiency and increasing the degree of the integration for these devices have been discussed. The latest achievements in the field of materials, geometry and the properties of the spin-transfer nano-oscillators, as well as the problems and prospects for the development of this technology have been considered. The analysis of theoretical and experimental works, in which the spin-gate structures have been used to perform the logical operations of Boolean and non-Boolean logic, has been carried out. It has been shown how the probabilistic nature of the unstable switching of spin gates is used in the op-eration of the unconventional computing systems, namely, neuromorphic or Bayesian networks. The principles of operation of the spin valves as magnetic biosensors have been considered and the advantages of their application have been discussed.

scholarly journals A Survey of ReRAM-Based Architectures for Processing-In-Memory and Neural Networks

2018 ◽  
Vol 1 (1) ◽  
pp. 75-114 ◽  
Author(s):  
Sparsh Mittal
Keyword(s):  
Machine Learning ◽  
Random Access ◽  
Random Access Memory ◽  
Resistive Random Access Memory ◽  
Low Energy ◽  
Power Budget ◽  
Access Memory ◽  
Computing Systems ◽  
Data Movement ◽  
Similarities And Differences

As data movement operations and power-budget become key bottlenecks in the design of computing systems, the interest in unconventional approaches such as processing-in-memory (PIM), machine learning (ML), and especially neural network (NN)-based accelerators has grown significantly. Resistive random access memory (ReRAM) is a promising technology for efficiently architecting PIM- and NN-based accelerators due to its capabilities to work as both: High-density/low-energy storage and in-memory computation/search engine. In this paper, we present a survey of techniques for designing ReRAM-based PIM and NN architectures. By classifying the techniques based on key parameters, we underscore their similarities and differences. This paper will be valuable for computer architects, chip designers and researchers in the area of machine learning.

scholarly journals Mapping Datasets to Object Storage System

2020 ◽  
Vol 245 ◽  
pp. 04037
Author(s):  
Xiaowei Aaron Chu ◽  
Jeff LeFevre ◽  
Aldrin Montana ◽  
Dana Robinson ◽  
Quincey Koziol ◽  
...  
Keyword(s):  
Storage Systems ◽  
Distributed Storage ◽  
Storage System ◽  
Random Access ◽  
Data Partitioning ◽  
Data Layout ◽  
Storage Devices ◽  
Storage Servers ◽  
Non Volatile Memory ◽  
Volatile Memory

Access libraries such as ROOT[1] and HDF5[2] allow users to interact with datasets using high level abstractions, like coordinate systems and associated slicing operations. Unfortunately, the implementations of access libraries are based on outdated assumptions about storage systems interfaces and are generally unable to fully benefit from modern fast storage devices. For example, access libraries often implement buffering and data layout that assume that large, single-threaded sequential access patterns are causing less overall latency than small parallel random access: while this is true for spinning media, it is not true for flash media. The situation is getting worse with rapidly evolving storage devices such as non-volatile memory and ever larger datasets. This project explores distributed dataset mapping infrastructures that can integrate and scale out existing access libraries using Ceph’s extensible object model, avoiding re-implementation or even modifications of these access libraries as much as possible. These programmable storage extensions coupled with our distributed dataset mapping techniques enable: 1) access library operations to be offloaded to storage system servers, 2) the independent evolution of access libraries and storage systems and 3) fully leveraging of the existing load balancing, elasticity, and failure management of distributed storage systems like Ceph. They also create more opportunities to conduct storage server-local optimizations specific to storage servers. For example, storage servers might include local key/value stores combined with chunk stores that require different optimizations than a local file system. As storage servers evolve to support new storage devices like non-volatile memory, these server-local optimizations can be implemented while minimizing disruptions to applications. We will report progress on the means by which distributed dataset mapping can be abstracted over particular access libraries, including access libraries for ROOT data, and how we address some of the challenges revolving around data partitioning and composability of access operations.

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