Investigation of Anti-SEB Capability of 160 V Power MOSFET Device with Multiple Buffer Layer

2021 ◽  
Author(s):  
Wanting Yang ◽  
Dongqing Hu ◽  
Xintian Zhou ◽  
Xinyu Li ◽  
Xingyu Fang ◽  
...  
Keyword(s):  
Buffer Layer ◽  
Power Mosfet

Normally Off GaN Power MOSFET Grown on Sapphire Substrate With Highly Resistive Undoped Buffer Layer

2012 ◽  
Vol 33 (10) ◽  
pp. 1429-1431 ◽  
Author(s):  
Jae-Hoon Lee ◽  
Jae-Hyun Jeong ◽  
Jung-Hee Lee
Keyword(s):  
Buffer Layer ◽  
Sapphire Substrate ◽  
Power Mosfet

In-Situ Study of NiO Growth on Textured Nickel Tape Using Environmental Scanning Electron Microscope (ESEM) and Hot Stage

2001 ◽  
Vol 7 (S2) ◽  
pp. 1276-1277
Author(s):  
Y. Akin ◽  
R.E. Goddard ◽  
W. Sigmund ◽  
Y.S. Hascicek
Keyword(s):  
Buffer Layer ◽  
Lattice Mismatch ◽  
Sol Gel ◽  
Surface Oxidation ◽  
Dip Coating ◽  
Buffer Layers ◽  
Superconducting Film ◽  
Environmental Scanning ◽  
Cold Rolling And Annealing

Deposition of highly textured ReBa2Cu3O7−δ (RBCO) films on metallic substrates requires a buffer layer to prevent chemical reactions, reduce lattice mismatch between metallic substrate and superconducting film layer, and to prevent diffusion of metal atoms into the superconductor film. Nickel tapes are bi-axially textured by cold rolling and annealing at appropriate temperature (RABiTS) for epitaxial growth of YBa2Cu3O7−δ (YBCO) films. As buffer layers, several oxide thin films and then YBCO were coated on bi-axially textured nickel tapes by dip coating sol-gel process. Biaxially oriented NiO on the cube-textured nickel tape by a process named Surface-Oxidation- Epitaxy (SEO) has been introduced as an alternative buffer layer. in this work we have studied in situ growth of nickel oxide by ESEM and hot stage.Representative cold rolled nickel tape (99.999%) was annealed in an electric furnace under 4% hydrogen-96% argon gas mixture at 1050°C to get bi-axially textured nickel tape.

Microcrystalline (Si,Ge):H Solar Cells

2003 ◽  
Vol 762 ◽  
Author(s):  
Jianhua Zhu ◽  
Vikram L. Dalal
Keyword(s):  
Solar Cells ◽  
Buffer Layer ◽  
Quantum Efficiency ◽  
Fill Factor ◽  
Open Circuit Voltage ◽  
Defect Density ◽  
Cell Structure ◽  
Open Circuit ◽  
Base Layer ◽  
Ecr Plasma

AbstractWe report on the growth and properties of microcrystalline Si:H and (Si,Ge):H solar cells on stainless steel substrates. The solar cells were grown using a remote, low pressure ECR plasma system. In order to crystallize (Si,Ge), much higher hydrogen dilution (∼40:1) had to be used compared to the case for mc-Si:H, where a dilution of 10:1 was adequate for crystallization. The solar cell structure was of the p+nn+ type, with light entering the p+ layer. It was found that it was advantageous to use a thin a-Si:H buffer layer at the back of the cells in order to reduce shunt density and improve the performance of the cells. A graded gap buffer layer was used at the p+n interface so as to improve the open-circuit voltage and fill factor. The open circuit voltage and fill factor decreased as the Ge content increased. Quantum efficiency measurements indicated that the device was indeed microcrystalline and followed the absorption characteristics of crystalline ( Si,Ge). As the Ge content increased, quantum efficiency in the infrared increased. X-ray measurements of films indicated grain sizes of ∼ 10nm. EDAX measurements were used to measure the Ge content in the films and devices. Capacitance measurements at low frequencies ( ~100 Hz and 1 kHz) indicated that the base layer was indeed behaving as a crystalline material, with classical C(V) curves. The defect density varied between 1x1016 to 2x1017/cm3, with higher defects indicated as the Ge concentration increased.

Carrier Redistribution Analysis of Gate-Biased SiC Power-MOSFET Using Super-Higher-Order Scanning Nonlinear Dielectric Microscopy

2015 ◽  
Author(s):  
Norimichi Chinone ◽  
Yasuo Cho
Keyword(s):  
Cross Section ◽  
Measurement System ◽  
Higher Order ◽  
Depletion Layer ◽  
Gate Bias ◽  
Power Mosfet ◽  
Nonlinear Dielectric ◽  
Voltage Dependent ◽  
Carrier Redistribution ◽  
Source Voltage

Abstract Gate-bias dependent depletion layer distribution and carrier distributions in cross-section of SiC power MOSFET were measured by newly developed measurement system based on super-higher-order scanning nonlinear dielectric microscope. The results visualized gate-source voltage dependent redistribution of depletion layer and carrier.

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