scholarly journals SEAMS

2021 ◽  
Vol 20 (5) ◽  
pp. 1-26
Author(s):  
Biswadip Maity ◽  
Bryan Donyanavard ◽  
Anmol Surhonne ◽  
Amir Rahmani ◽  
Andreas Herkersdorf ◽  
...  
Keyword(s):  
Memory Hierarchy ◽  
Main Memory ◽  
Management Policy ◽  
Additional Energy ◽  
Approximation Techniques ◽  
Design Time ◽  
On Chip ◽  
Quality Threshold ◽  
Application Developers

Memory approximation techniques are commonly limited in scope, targeting individual levels of the memory hierarchy. Existing approximation techniques for a full memory hierarchy determine optimal configurations at design-time provided a goal and application. Such policies are rigid: they cannot adapt to unknown workloads and must be redesigned for different memory configurations and technologies. We propose SEAMS: the first self-optimizing runtime manager for coordinating configurable approximation knobs across all levels of the memory hierarchy. SEAMS continuously updates and optimizes its approximation management policy throughout runtime for diverse workloads. SEAMS optimizes the approximate memory configuration to minimize energy consumption without compromising the quality threshold specified by application developers. SEAMS can (1) learn a policy at runtime to manage variable application quality of service ( QoS ) constraints, (2) automatically optimize for a target metric within those constraints, and (3) coordinate runtime decisions for interdependent knobs and subsystems. We demonstrate SEAMS’ ability to efficiently provide functions (1)–(3) on a RISC-V Linux platform with approximate memory segments in the on-chip cache and main memory. We demonstrate SEAMS’ ability to save up to 37% energy in the memory subsystem without any design-time overhead. We show SEAMS’ ability to reduce QoS violations by 75% with < 5% additional energy.

Systematic approaches in water management: Aquatic outlook and decision support systems combining monitoring, research, policy analysis and information technology

1996 ◽  
Vol 34 (12) ◽  
pp. 9-16 ◽  
Author(s):  
J. de Jong ◽  
J. T. van Buuren ◽  
J. P. A. Luiten
Keyword(s):  
Water Management ◽  
Policy Analysis ◽  
Research Policy ◽  
Human Life ◽  
Management Policy ◽  
Ecological Aspects ◽  
Management Plans ◽  
Water Management Plans ◽  
Life On Earth

Sustained developments is the target of almost every modern water management policy. Sustainability is focused on human life and on the ecological quality of our environment. Both aspects are essential for life on earth. Within a river catchment area this means that well balanced relations have to be laid between human activities and ecological aspects in the involved areas. Policy analysis is especially looking for the most efficient way to analyse and to overcome bottlenecks. In The Netherlands project “The Aquatic Outlook” all these elements are worked out in a nationwide scale, providing the scientific base and policy analysis from which future water management plans can be derived.

EXPLOITING THE MEMORY HIERARCHY OF MULTICORE SYSTEMS FOR PARALLEL TRIANGULATION REFINEMENT

2012 ◽  
Vol 22 (03) ◽  
pp. 1250007 ◽  
Author(s):  
PEDRO RODRÍGUEZ ◽  
MARÍA CECILIA RIVARA ◽  
ISAAC D. SCHERSON
Keyword(s):  
Parallel Implementation ◽  
Memory Hierarchy ◽  
Random Selection ◽  
Multicore Systems ◽  
Algorithm Performance ◽  
Bisection Algorithm ◽  
Improve Algorithm ◽  
Triangulation Refinement ◽  
Selection Of

A novel parallelization of the Lepp-bisection algorithm for triangulation refinement on multicore systems is presented. Randomization and wise use of the memory hierarchy are shown to highly improve algorithm performance. Given a list of selected triangles to be refined, random selection of candidates together with pre-fetching of Lepp-submeshes lead to a scalable and efficient multi-core parallel implementation. The quality of the refinement is shown to be preserved.

Late Breaking Results: Building an On-Chip Deep Learning Memory Hierarchy Brick by Brick

2020 ◽  
Author(s):  
Isak Edo Vivancos ◽  
Sayeh Sharify ◽  
Milos Nikolic ◽  
Ciaran Bannon ◽  
Mostafa Mahmoud ◽  
...  
Keyword(s):  
Deep Learning ◽  
Memory Hierarchy ◽  
On Chip

scholarly journals Intellectual Capital of a Trading Company: Comprehensive Analysis Based on Reporting

2020 ◽  
Vol 12 (17) ◽  
pp. 7095
Author(s):  
Oksana Pirogova ◽  
Olga Voronova ◽  
Tatyana Khnykina ◽  
Vladimir Plotnikov
Keyword(s):  
Content Analysis ◽  
Intellectual Capital ◽  
Value Added ◽  
Management Policy ◽  
Annual Reports ◽  
Trading Company ◽  
Significant Relationships ◽  
The Subject ◽  
The Russian Federation

The study is devoted to the analysis of the efficiency of use and the effectiveness of disclosing the intellectual capital (IC) of a trading company operating in the market of the Russian Federation. The subject of the research is an assessment of the quality of disclosure of information about the IC company involved in the creation of financial results of activities and the growth of the company’s value. The study examines the assessment of IC and the search for links between the involvement of IC in the formation of the financial result of a trading company and the degree of its reflection in the company’s annual reports. Methods of using intellectual value-added coefficients (VAIC) such as the trademark logo (written as ™), Calculated Intangible Value (CIV) and content analysis of the company’s annual reports are used to assess the IC and its elements. The influence of IC and its components, on the financial results of a trading company are also investigated and calculated using various methods. It is shown that there are no statistically significant relationships between the assessments of IC and its elements obtained using financial ratios, and those obtained using content analysis. This indicates that the opinions and assessments of the heads of a trading company regarding IC are formed regardless of the size of IC involved in the formation of economic results and testifies to the absence of an effective investment management policy in the studied company. Some of the results obtained confirm the trends in IC structures previously observed for companies in other industries. The results also indicate that the existing system for preparing annual reports does not sufficiently consider the size, dynamics and efficiency of using the intangible assets of a trading company. The results of this study are likely to be useful to management and academics.

scholarly journals Direct Ink Writing of Materials for Electronics-Related Applications: A Mini Review

2021 ◽  
Vol 8 ◽  
Author(s):  
Zhenzhong Hou ◽  
Hai Lu ◽  
Ying Li ◽  
Laixia Yang ◽  
Yang Gao
Keyword(s):  
Human Life ◽  
Electronic Devices ◽  
Electronic Components ◽  
Direct Ink Writing ◽  
Recent Developments ◽  
Print Materials ◽  
On Chip ◽  
Functional Components ◽  
Printing Techniques

Recently, the fabrication of electronics-related components via direct ink writing (DIW) has attracted much attention. Compared to the conventionally fabricated electronic components, DIW-printed ones have more complicated structures, higher accuracy, improved efficiency, and even enhanced performances that arise from well-designed architectures. The DIW technology allows directly print materials on a variety of flat substrates, even a conformal one, well suiting them to applications such as wearable devices and on-chip integrations. Here, recent developments in DIW printing of emerging components for electronics-related applications are briefly reviewed, including electrodes, electronic circuits, and functional components. The printing techniques, processes, ink materials, advantages, and properties of DIW-printed architectures are discussed. Finally, the challenges and outlooks on the manufacture of 3D structured electronic devices by DIW are outlined, pointing out future designs and developments of DIW technology for electronics-related applications. The combination of DIW and electronic devices will help to improve the quality of human life and promote the development of science and society.

FEATURES OF THE FORMATION AND MANAGEMENT OF OWN CAPITAL: PRINCIPLES OF DEVELOPING A SELF-FINANCING POLICY

2021 ◽  
Author(s):  
Елена Сергеевна Симонова
Keyword(s):  
Market Economy ◽  
Stable State ◽  
Management Policy ◽  
Financing Policy ◽  
Equity Management

Статья посвящена раскрытию темы об особенностях формирования политики управления собственным капиталом. Поскольку от качества управления собственными ресурсами зависит дальнейшая деятельность предприятия, его стабильное и устойчивое состояние в условиях рыночной экономики. The article is devoted to the disclosure of the topic about the peculiarities of the formation of the equity management policy. Since the quality of the management of its own resources depends on the further activity of the enterprise, its stable and stable state in a market economy.

Towards a Hybrid Modeling

2015 ◽  
pp. 422-442
Keyword(s):  
Learning Environment ◽  
Hybrid Approach ◽  
Hybrid Modeling ◽  
Management Policy ◽  
Computer Supported Collaborative Learning ◽  
Web 3.0 ◽  
Potential Case ◽  
Learning Scenarios ◽  
Collaborative Learning Environment

This chapter introduces the reader to Part IV of the book, proposing and discussing a hybrid approach that may serve, not only to synthesize and represent knowledge obtained from the data, but also to explore possible future online learning environment (OLE) states, given different management, policy or environmental scenarios. Pragmatically, this chapter explores the potentiality of the quality of collaboration (QoC) within an Internet-based computer-supported collaborative learning environment and quality of interaction (QoI) with a LMS, both involving fuzzy logic-based modeling, as vehicles to improve the personalization and intelligence of an OLE. Furthermore, QoC and QoI can form the basis for a more pragmatic approach of OLEs under the perspective of semantic Web 3.0, within the context of Higher Education. Finally, a potential case study of the examined hybrid modeling, referring to the “i-TREASURES” European FP7 Programme, is discussed, to explore its applicability and functionality under pragmatic learning scenarios.

Dynamically Reconfigurable Networks-on-Chip Using Runtime Adaptive Routers

2010 ◽  
pp. 28-66 ◽  
Author(s):  
Mário P. Véstias ◽  
Horácio C. Neto
Keyword(s):  
Quality Of Service ◽  
Power Consumption ◽  
First Generation ◽  
Networks On Chip ◽  
Dynamically Reconfigurable ◽  
Systems On Chip ◽  
High Bandwidth ◽  
Area Occupation ◽  
On Chip

The recent advances in IC technology have made it possible to implement systems with dozens or even hundreds of cores in a single chip. With such a large number of cores communicating with each other there is a strong pressure over the communication infrastructure to deliver high bandwidth, low latency, low power consumption and quality of service to guarantee real-time functionality. Networks-on-Chip are definitely becoming the only acceptable interconnection structure for today’s multiprocessor systems-on-chip (MPSoC). The first generation of NoC solutions considers a regular topology, typically a 2D mesh. Routers and network interfaces are mainly homogeneous so that they can be easily scaled up and modular design is facilitated. All advantages of a NoC infrastructure were proved with this first generation of NoC solutions. However, NoCs have a relative area and speed overhead. Application specific systems can benefit from heterogeneous communication infrastructures providing high bandwidth in a localized fashion where it is needed with improved area. The efficiency of both homogeneous and heterogeneous solutions can be improved if runtime changes are considered. Dynamically or runtime reconfigurable NoCs are the second generation of NoCs since they represent a new set of benefits in terms of area overhead, performance, power consumption, fault tolerance and quality of service compared to the previous generation where the architecture is decided at design time. This chapter discusses the static and runtime customization of routers and presents results with networks-on-chip with static and adaptive routers. Runtime adaptive techniques are analyzed and compared to each other in terms of area occupation and performance. The results and the discussion presented in this chapter show that dynamically adaptive routers are fundamental in the design of NoCs to satisfy the requirements of today’s systems-on-chip.

Underfill Dispensing for 3D Die Stacking with Through Silicon Vias

2012 ◽  
Vol 2012 (1) ◽  
pp. 000548-000553 ◽  
Author(s):  
Fuliang Le ◽  
S. W. Ricky Lee ◽  
Jingshen Wu ◽  
Matthew M. F. Yuen
Keyword(s):  
Flip Chip ◽  
Through Silicon Vias ◽  
Flip Chips ◽  
Solder Bumps ◽  
Die Stacking ◽  
Chip Carrier ◽  
On Chip ◽  
Silicon Vias ◽  
3D Package

In this paper, a 3D stacked-die package is developed for the miniaturization and integration of electronic devices. The developed package has a stacked flip-chip-on-chip structure and eight flip chips are arranged in four vertical layers using four silicon chip carriers with through silicon vias (TSVs). In each layer, two flip chips are mounted on the silicon chip carrier with 100 um solder bumps, and multiple TSVs are fabricated in each silicon chip carrier for underfill dispensing purpose. The 3D module with four stacked layers is sequentially assembled by the standard surface mount reflow process and finally mounted to a substrate. In the underfill process, conventional I-pass underfill is used to fill up the gaps of the bottom two layers as it has relatively fast spreading speed. For the top two chip carriers, underfill is dispensed through TSVs to fill the gaps. Unlike the conventional underfill process, the encapsulant in this case would not flow in the gaps by the capillary effect unless the dispensed materials can obtain enough kinetic energy to overcome the surface tension at the end of TSVs, and thus, smooth sidewall, proper dispensing settings and optimized TSV pattern are needed. After underfill, detailed inspections are performed to verify the quality of encapsulation. The results show that the combined I-pass/TSV underfill process gives void-free encapsulation and perfect fillets for the stacked 3D package.

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