Replication Package for Paper: LLHD: A Multi-level Intermediate Representation for Hardware Description Languages

2020 ◽  
Author(s):  
Fabian Schuiki ◽  
Andreas Kurth ◽  
Tobias Grosser ◽  
Luca Benini
Keyword(s):  
Intermediate Representation ◽  
Hardware Description Languages ◽  
Hardware Description ◽  
Multi Level ◽  
Description Languages

scholarly journals Functional Verification of Large-integers Circuits using a Cosimulation-based Approach

2017 ◽  
Vol 7 (4) ◽  
pp. 2192
Author(s):  
Nejmeddine Alimi ◽  
Younes Lahbib ◽  
Mohsen Machhout ◽  
Rached Tourki
Keyword(s):  
Good Evidence ◽  
Modular Arithmetic ◽  
Functional Verification ◽  
Hardware Description Languages ◽  
Abstraction Level ◽  
Hardware Description ◽  
Multi Level ◽  
Description Languages ◽  
High Level ◽  
Real Challenge

Cryptography and computational algebra designs are complex systems based on modular arithmetic and build on multi-level modules where bit-width is generally larger than 64-bit. Because of their particularity, such designs pose a real challenge for verification, in part because large-integer’s functions are not supported in actual hardware description languages (HDLs), therefore limiting the HDL testbench utility. In another hand, high-level verification approach proved its efficiency in the last decade over HDL testbench technique by raising the latter at a higher abstraction level. In this work, we propose a high-level platform to verify such designs, by leveraging the capabilities of a popular tool (Matlab/Simulink) to meet the requirements of a cycle accurate verification without bit-size restrictions and in multi-level inside the design architecture. The proposed high-level platform is augmented by an assertion-based verification to complete the verification coverage. The platform experimental results of the testcase provided good evidence of its performance and re-usability.

Sign in / Sign up

Export Citation Format

Share Document