scholarly journals Characterizing processor architectures for programmable network interfaces

2000 ◽  
Author(s):  
Patrick Crowley ◽  
Marc E. Fluczynski ◽  
Jean-Loup Baer ◽  
Brian N. Bershad
Keyword(s):  
Processor Architectures ◽  
Programmable Network ◽  
Network Interfaces

Software-Based Failure Detection and Recovery in Programmable Network Interfaces

2007 ◽  
Vol 18 (11) ◽  
pp. 1539-1550 ◽  
Author(s):  
Yizheng Zhou ◽  
Vijay Lakamraju ◽  
Israel Koren ◽  
C. M. Krishna
Keyword(s):  
Failure Detection ◽  
Programmable Network ◽  
Network Interfaces

Workloads for Programmable Network Interfaces

2000 ◽  
pp. 135-147 ◽  
Author(s):  
Patrick Crowley ◽  
Marc E. Fiuczynski ◽  
Jean-Loup Baer ◽  
Brian Bershad
Keyword(s):  
Programmable Network ◽  
Network Interfaces

The IEEE P1520 standards initiative for programmable network interfaces

1998 ◽  
Vol 36 (10) ◽  
pp. 64-70 ◽  
Author(s):  
J. Biswas ◽  
A.A. Lazar ◽  
J.-F. Huard ◽  
Koonseng Lim ◽  
S. Mahjoub ◽  
...  
Keyword(s):  
Programmable Network ◽  
Network Interfaces

scholarly journals Efficient local locking for massively multithreaded in-memory hash-based operators

2021 ◽  
Author(s):  
Bashar Romanous ◽  
Skyler Windh ◽  
Ildar Absalyamov ◽  
Prerna Budhkar ◽  
Robert Halstead ◽  
...  
Keyword(s):  
Relational Databases ◽  
Aggregation Operators ◽  
Main Memory ◽  
Paradigm Shifts ◽  
Multithreaded Processors ◽  
Cache Hierarchies ◽  
Processor Architectures ◽  
Spatial Locality ◽  
Content Addressable Memories ◽  
Multi Core Processor

AbstractThe join and group-by aggregation are two memory intensive operators that are affecting the performance of relational databases. Hashing is a common approach used to implement both operators. Recent paradigm shifts in multi-core processor architectures have reinvigorated research into how the join and group-by aggregation operators can leverage these advances. However, the poor spatial locality of the hashing approach has hindered performance on multi-core processor architectures which rely on using large cache hierarchies for latency mitigation. Multithreaded architectures can better cope with poor spatial locality by masking memory latency with many outstanding requests. Nevertheless, the number of parallel threads, even in the most advanced multithreaded processors, such as UltraSPARC, is not enough to fully cover the main memory access latency. In this paper, we explore the hardware re-configurability of FPGAs to enable deeper execution pipelines that maintain hundreds (instead of tens) of outstanding memory requests across four FPGAs-drastically increasing concurrency and throughput. We present two end-to-end in-memory accelerators for the join and group-by aggregation operators using FPGAs. Both accelerators use massive multithreading to mask long memory delays of traversing linked-list data structures, while concurrently managing hundreds of thread states across four FPGAs locally. We explore how content addressable memories can be intermixed within our multithreaded designs to act as a synchronizing cache, which enforces locks and merges jobs together before they are written to memory. Throughput results for our hash-join operator accelerator show a speedup between 2$$\times $$ × and 3.4$$\times $$ × over the best multi-core approaches with comparable memory bandwidths on uniform and skewed datasets. The accelerator for the hash-based group-by aggregation operator demonstrates that leveraging CAMs achieves average speedup of 3.3$$\times $$ × with a best case of 9.4$$\times $$ × in terms of throughput over CPU implementations across five types of data distributions.

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