Better Bounds for Block Cipher Modes of Operation via Nonce-Based Key Derivation

2017 ◽  
Author(s):  
Shay Gueron ◽  
Yehuda Lindell
Keyword(s):  
Block Cipher ◽  
Modes Of Operation ◽  
Key Derivation

Symmetric Encryption

2017 ◽  
Author(s):  
Keith M. Martin
Keyword(s):  
Stream Cipher ◽  
Block Cipher ◽  
Block Ciphers ◽  
Data Encryption ◽  
Advanced Encryption Standard ◽  
Symmetric Encryption ◽  
Modes Of Operation ◽  
Data Encryption Standard ◽  
Different Types ◽  
History Of

In this chapter, we focus on symmetric encryption. We begin by identifying two different types of symmetric encryption algorithm, namely, stream and block ciphers. We discuss the basic idea behind a stream cipher and consider their properties and applications. We then introduce block ciphers. We focus on two extremely important and influential block cipher algorithms, the Data Encryption Standard and the Advanced Encryption Standard, discussing the history of their development as well as their basic design. We then introduce the modes of operation of a block cipher, explaining why different modes have been proposed. We examine in detail four of the most well-established modes of operation and their core properties, as well as classifying other modes of operation.

scholarly journals ACE: ARIA-CTR Encryption for Low-End Embedded Processors

Sensors ◽  
2020 ◽  
Vol 20 (13) ◽  
pp. 3788 ◽  
Author(s):  
Hwajeong Seo ◽  
Hyeokdong Kwon ◽  
Hyunji Kim ◽  
Jaehoon Park
Keyword(s):  
Diffusion Layer ◽  
High Speed ◽  
Block Cipher ◽  
Embedded Processors ◽  
Embedded Processor ◽  
Modes Of Operation ◽  
Risc Processor ◽  
Mode Of Operation ◽  
Security Levels

In this paper, we present the first optimized implementation of ARIA block cipher on low-end 8-bit Alf and Vegard’s RISC processor (AVR) microcontrollers. To achieve high-speed implementation, primitive operations, including rotation operation, a substitute layer, and a diffusion layer, are carefully optimized for the target low-end embedded processor. The proposed ARIA implementation supports the electronic codebook (ECB) and the counter (CTR) modes of operation. In particular, the CTR mode of operation is further optimized with the pre-computed table of two add-round-key, one substitute layer, and one diffusion layer operations. Finally, the proposed ARIA-CTR implementations on 8-bit AVR microcontrollers achieved 187.1, 216.8, and 246.6 clock cycles per byte for 128-bit, 192-bit, and 256-bit security levels, respectively. Compared with previous reference implementations, the execution timing is improved by 69.8%, 69.6%, and 69.5% for 128-bit, 192-bit, and 256-bit security levels, respectively.

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