High-Performance Instruction Scheduling Circuits for Superscalar Out-of-Order Soft Processors

2018 ◽  
Vol 11 (1) ◽  
pp. 1-22 ◽  
Author(s):  
Henry Wong ◽  
Vaughn Betz ◽  
Jonathan Rose
Keyword(s):  
High Performance ◽  
Instruction Scheduling ◽  
Performance Instruction

scholarly journals Static Instruction Scheduling for High Performance on Limited Hardware

2018 ◽  
Vol 67 (4) ◽  
pp. 513-527
Author(s):  
Kim-Anh Tran ◽  
Trevor E. Carlson ◽  
Konstantinos Koukos ◽  
Magnus Sjalander ◽  
Vasileios Spiliopoulos ◽  
...  
Keyword(s):  
High Performance ◽  
Instruction Scheduling

scholarly journals A Ubiquitous Processor Built-in a Waved Multifunctional Unit

1970 ◽  
Vol 4 (1) ◽  
pp. 1-7
Author(s):  
Masa-aki Fukase ◽  
Tomoaki Sato
Keyword(s):  
Mobile Applications ◽  
High Performance ◽  
Scale Up ◽  
Instruction Scheduling ◽  
Instruction Level Parallelism ◽  
Floating Point ◽  
Ubiquitous Systems ◽  
Wide Range ◽  
Wave Pipelining ◽  
Level Parallelism

In developing cutting edge VLSI processors, parallelism is one of the most important global standard strategies to achieve power conscious high performance. These features are more critical for ubiquitous systems with great demands for multimedia mobile processing. Then, one of most important issues for ubiquitous systems is instruction scheduling, because floating point units indispensable for multimedia mobile applications take longer latency than integer units. Although software parallelism has been inevitable to fully utilize hardware parallelism between regular scalar units, it has been really awkward. Thus, we describe in this article a double scheme to achieve instruction scheduling free ILP (instruction level parallelism) and apply the double scheme to a ubiquitous processor HCgorilla we have so far developed. The double scheme is the multifunctionalization of scalar units and making a resultant multifunctional unit (MFU) wave-pipeline. The multifunctionalization frees the instruction scheduling, and the wave-pipelining recovers the reduction of clock speed to be caused by the scale up of a multifunctional circuit. HCgorilla built-in the waved MFU is promising for wide-range dynamic ILP at a rate higher than regular processors.

Designing high performance instruction caches in VLSI

1990 ◽  
Vol 30 (1-5) ◽  
pp. 135-142
Author(s):  
J.E.H.M. Bormans ◽  
W.J. Withagen ◽  
F.P.M. Budzelaar ◽  
M.P.J. Stevens
Keyword(s):  
High Performance ◽  
Instruction Caches ◽  
Performance Instruction

Adding static data dependence collapsing to a high-performance instruction scheduler

2001 ◽  
Vol 47 (8) ◽  
pp. 727-745
Author(s):  
Fleur L. Steven ◽  
Colin Egan ◽  
Richard D. Potter ◽  
Gordon B. Steven
Keyword(s):  
High Performance ◽  
Data Dependence ◽  
Static Data ◽  
Instruction Scheduler ◽  
Performance Instruction
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