Task-FIFO Co-Scheduling of Streaming Applications on MPSoCs with Predictable Memory Hierarchy

Qi Tang; Twan Basten; Marc Geilen; Sander Stuijk; Ji-Bo Wei

doi:10.1145/3038484

Task-FIFO Co-Scheduling of Streaming Applications on MPSoCs with Predictable Memory Hierarchy

ACM Transactions on Embedded Computing Systems ◽

10.1145/3038484 ◽

2017 ◽

Vol 16 (2) ◽

pp. 1-25 ◽

Cited By ~ 2

Author(s):

Qi Tang ◽

Twan Basten ◽

Marc Geilen ◽

Sander Stuijk ◽

Ji-Bo Wei

Keyword(s):

Memory Hierarchy ◽

Streaming Applications

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Task-FIFO Co-scheduling of Streaming Applications on MPSoCs with Predictable Memory Hierarchy

2015 15th International Conference on Application of Concurrency to System Design ◽

10.1109/acsd.2015.9 ◽

2015 ◽

Cited By ~ 1

Author(s):

Qi Tang ◽

Twan Basten ◽

Marc Geilen ◽

Sander Stuijk ◽

Ji-Bo Wei

Keyword(s):

Memory Hierarchy ◽

Streaming Applications

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Probabilistic Performance Modelling when Using Partial Reconfiguration to Accelerate Streaming Applications with Non-deterministic Task Scheduling

Lecture Notes in Computer Science - Applied Reconfigurable Computing ◽

10.1007/978-3-030-17227-5_7 ◽

2019 ◽

pp. 81-95

Author(s):

Bruno da Silva ◽

An Braeken ◽

Abdellah Touhafi

Keyword(s):

Task Scheduling ◽

Partial Reconfiguration ◽

Performance Modelling ◽

Streaming Applications

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MILC Code Performance on High End CPU and GPU Supercomputer Clusters

EPJ Web of Conferences ◽

10.1051/epjconf/201817502009 ◽

2018 ◽

Vol 175 ◽

pp. 02009

Author(s):

Carleton DeTar ◽

Steven Gottlieb ◽

Ruizi Li ◽

Doug Toussaint

Keyword(s):

Conjugate Gradient ◽

Memory Hierarchy ◽

Xeon Phi ◽

Intel Xeon Phi ◽

Code Performance ◽

Recent Developments ◽

Knights Landing ◽

Many Core ◽

Intel Xeon

With recent developments in parallel supercomputing architecture, many core, multi-core, and GPU processors are now commonplace, resulting in more levels of parallelism, memory hierarchy, and programming complexity. It has been necessary to adapt the MILC code to these new processors starting with NVIDIA GPUs, and more recently, the Intel Xeon Phi processors. We report on our efforts to port and optimize our code for the Intel Knights Landing architecture. We consider performance of the MILC code with MPI and OpenMP, and optimizations with QOPQDP and QPhiX. For the latter approach, we concentrate on the staggered conjugate gradient and gauge force. We also consider performance on recent NVIDIA GPUs using the QUDA library.

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