Standard cell placement for even on-chip thermal distribution

1999 ◽  
Author(s):  
Ching-Han Tsai ◽  
Sung-Mo (Steve) Kang
Keyword(s):  
Standard Cell ◽  
Thermal Distribution ◽  
Cell Placement ◽  
On Chip

scholarly journals A Swarm Random Walk Based Method for the Standard Cell Placement Problem

2014 ◽  
Vol 2014 ◽  
pp. 1-11 ◽  
Author(s):  
Najwa Altwaijry ◽  
Mohamed El Bachir Menai
Keyword(s):  
Simulated Annealing ◽  
Random Walk ◽  
Hybrid Methods ◽  
Vlsi Design ◽  
Standard Cell ◽  
Placement Problem ◽  
Benchmark Suite ◽  
Cell Placement ◽  
On Chip ◽  
Min Cut

The standard cell placement (SCP) problem is a well-studied placement problem, as it is an important step in the VLSI design process. In SCP, cells are placed on chip to optimize some objectives, such as wirelength or area. The SCP problem is solved using mainly four basic methods: simulated annealing, quadratic placement, min-cut placement, and force-directed placement. These methods are adequate for small chip sizes. Nowadays, chip sizes are very large, and hence, hybrid methods are employed to solve the SCP problem instead of the original methods by themselves. This paper presents a new hybrid method for the SCP problem using a swarm intelligence-based (SI) method, called SwarmRW (swarm random walk), on top of a min-cut based partitioner. The resulting placer, called sPL (swarm placer), was tested on the PEKU benchmark suite and compared with several related placers. The obtained results demonstrate the effectiveness of the proposed approach and show that sPL can achieve competitive performance.

Modern Standard-cell Placement Techniques

2001 ◽  
pp. 45-87
Author(s):  
Xiaojian Yang ◽  
Elaheh Bozorgzadeh ◽  
Majid Sarrafzadeh ◽  
Maogang Wang
Keyword(s):  
Standard Cell ◽  
Cell Placement ◽  
Modern Standard

A Fully Standard-Cell Based On-Chip BTI and HCI Monitor with 6.2x BTI sensitivity and 3.6x HCI sensitivity at 7 nm Fin-FET Process

2018 ◽  
Author(s):  
Mitsuhiko Igarashi ◽  
Yuuki Uchida ◽  
Yoshio Takazawa ◽  
Yasumasa Tsukamoto ◽  
Koji Shibutani ◽  
...  
Keyword(s):  
Standard Cell ◽  
On Chip

scholarly journals Improved Parallel Legalization Schemes for Standard Cell Placement with Obstacles

Technologies ◽  
2018 ◽  
Vol 7 (1) ◽  
pp. 3
Author(s):  
Panagiotis Oikonomou ◽  
Antonios Dadaliaris ◽  
Kostas Kolomvatsos ◽  
Thanasis Loukopoulos ◽  
Athanasios Kakarountas ◽  
...  
Keyword(s):  
Target Function ◽  
Problem Formulation ◽  
Search Space ◽  
Standard Cell ◽  
Chip Area ◽  
Time Performance ◽  
Trade Offs ◽  
Cell Placement ◽  
Placement Algorithm ◽  
Algorithmic Approaches

In standard cell placement, a circuit is given consisting of cells with a standard height, (different widths) and the problem is to place the cells in the standard rows of a chip area so that no overlaps occur and some target function is optimized. The process is usually split into at least two phases. In a first pass, a global placement algorithm distributes the cells across the circuit area, while in the second step, a legalization algorithm aligns the cells to the standard rows of the power grid and alleviates any overlaps. While a few legalization schemes have been proposed in the past for the basic problem formulation, few obstacle-aware extensions exist. Furthermore, they usually provide extreme trade-offs between time performance and optimization efficiency. In this paper, we focus on the legalization step, in the presence of pre-allocated modules acting as obstacles. We extend two known algorithmic approaches, namely Tetris and Abacus, so that they become obstacle-aware. Furthermore, we propose a parallelization scheme to tackle the computational complexity. The experiments illustrate that the proposed parallelization method achieves a good scalability, while it also efficiently prunes the search space resulting in a superlinear speedup. Furthermore, this time performance comes at only a small cost (sometimes even improvement) concerning the typical optimization metrics.

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