Fine-granularity tile-level parallelism in non-volatile memory architecture with two-dimensional bank subdivision

2016 ◽  
Author(s):  
Matthew Poremba ◽  
Tao Zhang ◽  
Yuan Xie
Keyword(s):  
Two Dimensional ◽  
Memory Architecture ◽  
Non Volatile Memory ◽  
Volatile Memory ◽  
Level Parallelism

scholarly journals Two Dimensional Parity Check with Variable Length Error Detection Code for the Non-Volatile Memory of Smart Data

2018 ◽  
Vol 8 (8) ◽  
pp. 1211 ◽  
Author(s):  
Cihun-Siyong Gong ◽  
Yung-Chang Chang ◽  
Li-Ren Huang ◽  
Chih-Jen Yang ◽  
Kung-Ming Ji ◽  
...  
Keyword(s):  
Error Detection ◽  
Cosmic Ray ◽  
Variable Length ◽  
Automotive Electronics ◽  
Two Dimensional ◽  
Memory Protection ◽  
Non Volatile Memory ◽  
Smart Data ◽  
Volatile Memory ◽  
Detection Quality

This paper proposes a novel technology of memory protection for the Non-Volatile Memory (NVM), applied to smart sensors and smart data. Based on the asymmetry of failure rate between the statuses of bit-0 and bit-1 in the non-volatile memory, as a result of the pollution of the radiation of cosmic ray, a two-dimensional parity with variable length error detection code (2D-VLEDC) for memory protection is proposed. 2D-VLEDC has the feature of variable length of redundant bits varied with content of data word in the NVM. The experimental results show that the same error detection quality could be achieved with a 30% redundancy improvement by applying the proposed 2D-VLEDC. The proposed design is particularly suitable for the use of safety-related fields, such as the automotive electronics and industrial non-volatile memories involved in the industrial automation.

NVM Streaker: a fast and reconfigurable performance simulator for non-volatile memory-based memory architecture

2018 ◽  
Vol 74 (8) ◽  
pp. 3875-3903
Author(s):  
Danqi Hu ◽  
Fang Lv ◽  
Chenxi Wang ◽  
Hui-Min Cui ◽  
Lei Wang ◽  
...  
Keyword(s):  
Memory Architecture ◽  
Non Volatile Memory ◽  
Volatile Memory

scholarly journals RC-NVM: Dual-Addressing Non-Volatile Memory Architecture Supporting Both Row and Column Memory Accesses

2019 ◽  
Vol 68 (2) ◽  
pp. 239-254 ◽  
Author(s):  
Shuo Li ◽  
Nong Xiao ◽  
Peng Wang ◽  
Guangyu Sun ◽  
Xiaoyang Wang ◽  
...  
Keyword(s):  
Memory Architecture ◽  
Non Volatile Memory ◽  
Volatile Memory ◽  
Memory Accesses

scholarly journals Energy-Efficient Non-Von Neumann Computing Architecture Supporting Multiple Computing Paradigms for Logic and Binarized Neural Networks

2021 ◽  
Vol 11 (3) ◽  
pp. 29
Author(s):  
Tommaso Zanotti ◽  
Francesco Maria Puglisi ◽  
Paolo Pavan
Keyword(s):  
Neural Networks ◽  
High Performance ◽  
Random Access ◽  
Resistive Random Access Memory ◽  
Hardware Accelerators ◽  
Memory Architecture ◽  
Ultra Low Power ◽  
Von Neumann ◽  
Non Volatile Memory ◽  
Volatile Memory

Different in-memory computing paradigms enabled by emerging non-volatile memory technologies are promising solutions for the development of ultra-low-power hardware for edge computing. Among these, SIMPLY, a smart logic-in-memory architecture, provides high reconfigurability and enables the in-memory computation of both logic operations and binarized neural networks (BNNs) inference. However, operation-specific hardware accelerators can result in better performance for a particular task, such as the analog computation of the multiply and accumulate operation for BNN inference, but lack reconfigurability. Nonetheless, a solution providing the flexibility of SIMPLY while also achieving the high performance of BNN-specific analog hardware accelerators is missing. In this work, we propose a novel in-memory architecture based on 1T1R crossbar arrays, which enables the coexistence on the same crossbar array of both SIMPLY computing paradigm and the analog acceleration of the multiply and accumulate operation for BNN inference. We also highlight the main design tradeoffs and opportunities enabled by different emerging non-volatile memory technologies. Finally, by using a physics-based Resistive Random Access Memory (RRAM) compact model calibrated on data from the literature, we show that the proposed architecture improves the energy delay product by >103 times when performing a BNN inference task with respect to a SIMPLY implementation.

scholarly journals Comprehensive Performance Quasi-Non-Volatile Memory Compatible with Large-Scale Preparation by Chemical Vapor Deposition

Nanomaterials ◽  
2020 ◽  
Vol 10 (8) ◽  
pp. 1471
Author(s):  
Kun Yang ◽  
Hongxia Liu ◽  
Shulong Wang ◽  
Wenlong Yu ◽  
Tao Han
Keyword(s):  
Power Dissipation ◽  
Large Scale ◽  
Electronic Devices ◽  
Charge Storage ◽  
Two Dimensional ◽  
Large Scale Preparation ◽  
Two Dimensional Materials ◽  
Non Volatile Memory ◽  
Scale Preparation ◽  
Volatile Memory

Two-dimensional materials with atomic thickness have become candidates for wearable electronic devices in the future. Graphene and transition metal sulfides have received extensive attention in logic computing and sensing applications due to their lower power dissipation, so that their processes have been relatively mature for large-scale preparation. However, there are a few applications of two-dimensional materials in storage, which is not in line with the development trend of integration of storage and computing. Here, a charge storage quasi-non-volatile memory with a lanthanum incorporation high-k dielectric for next-generation memory devices is proposed. Thanks to the excellent electron capture capability of LaAlO3, the MoS2 memory exhibits a very comprehensive information storage capability, including robust endurance and ultra-fast write speed of 1 ms approximately. It is worth mentioning that it exhibits a long-term stable charge storage capacity (refresh time is about 1000 s), which is 105 times that of the dynamic random access memory (refresh time is on a milliseconds timescale) so that the unnecessary power dissipation greatly reduces caused by frequent refresh. In addition, its simple manufacturing process makes it compatible with various current two-dimensional electronic devices, which will greatly promote the integration of two-dimensional electronic computing.

scholarly journals Secure Object Stores (SOS): Non-Volatile Memory Architecture for Secure Computing

2016 ◽  
Vol 11 (3) ◽  
pp. 189-194
Author(s):  
Rodel Felipe Miguel ◽  
Sivaraman Sundaram ◽  
K. M. M. Aung
Keyword(s):  
Memory Architecture ◽  
Secure Computing ◽  
Non Volatile Memory ◽  
Volatile Memory

ECC-Based Bit-Write Reduction Code Generation for Non-Volatile Memory

2015 ◽  
Vol E98.A (12) ◽  
pp. 2494-2504 ◽  
Author(s):  
Masashi TAWADA ◽  
Shinji KIMURA ◽  
Masao YANAGISAWA ◽  
Nozomu TOGAWA
Keyword(s):  
Code Generation ◽  
Non Volatile Memory ◽  
Volatile Memory
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