Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits

Author(s):  
Atila Alvandpour ◽  
Per Larsson-Edefors ◽  
Christer Svensson
2000 ◽  
Vol 22 (3) ◽  
pp. 215-233 ◽  
Author(s):  
N. E. Evmorfopoulos ◽  
J. N. Avaritsiotis

A method for maximum power estimation in CMOS VLSI circuits is proposed. The method is based on extreme value theory and allows for the calculation of the upper end point of the probability distribution which is followed by the instantaneous power drawn from the supply bus. The main features of the method are the relatively small and circuitin-dependent subset of input patterns required for accurate prediction of maximum power and its simulative nature which ensures that no over-simplifying assumptions are made. Application of the proposed method to eight distributions, which come close to the behavior of power consumption in VLSI circuits, proved its superior capabilities with respect to existing methods.


2007 ◽  
Vol 16 (03) ◽  
pp. 455-465 ◽  
Author(s):  
MOSIN MONDAL ◽  
YEHIA MASSOUD

In the nanometer regime, crosstalk significantly impacts the dynamic power consumption of a chip. In this paper, we present a methodology for analyzing crosstalk-induced short-circuit power dissipation in cell-based digital designs. We introduce a new cell pre-characterization technique for facilitating the estimation of crosstalk-induced short-circuit power. Examples demonstrate that the presented methodology is three orders of magnitude faster than circuit simulators while the average error is as low as 3.5%.


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