Dataflow Graph Partitioning for Area-Efficient High-Level Synthesis with Systems Perspective

Sharad Sinha; Thambipillai Srikanthan

doi:10.1145/2660769

Dataflow Graph Partitioning for Area-Efficient High-Level Synthesis with Systems Perspective

ACM Transactions on Design Automation of Electronic Systems ◽

10.1145/2660769 ◽

2014 ◽

Vol 20 (1) ◽

pp. 1-18 ◽

Cited By ~ 4

Author(s):

Sharad Sinha ◽

Thambipillai Srikanthan

Keyword(s):

Graph Partitioning ◽

High Level Synthesis ◽

Dataflow Graph ◽

Systems Perspective ◽

High Level ◽

Area Efficient

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Dataflow graph partitioning for high level synthesis

22nd International Conference on Field Programmable Logic and Applications (FPL) ◽

10.1109/fpl.2012.6339265 ◽

2012 ◽

Cited By ~ 3

Author(s):

Sharad Sinha ◽

Thambipillai Srikanthan

Keyword(s):

Graph Partitioning ◽

High Level Synthesis ◽

Dataflow Graph ◽

High Level

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SynDFG: Synthetic dataflow graph generator for high-level synthesis

2015 6th Asia Symposium on Quality Electronic Design (ASQED) ◽

10.1109/acqed.2015.7274006 ◽

2015 ◽

Author(s):

Sharad Sinha ◽

Wei Zhang

Keyword(s):

High Level Synthesis ◽

Dataflow Graph ◽

High Level

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Area-efficient pipelining for FPGA-targeted high-level synthesis

Proceedings of the 52nd Annual Design Automation Conference on - DAC '15 ◽

10.1145/2744769.2744801 ◽

2015 ◽

Cited By ~ 10

Author(s):

Ritchie Zhao ◽

Mingxing Tan ◽

Steve Dai ◽

Zhiru Zhang

Keyword(s):

High Level Synthesis ◽

High Level ◽

Area Efficient

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System-level verification on high-level synthesis of dataflow graph

2006 IEEE International Conference on Acoustics Speed and Signal Processing Proceedings ◽

10.1109/iscas.2006.1692708 ◽

2006 ◽

Author(s):

Tsung-Hsi Chiang ◽

Lan-Rong Dung

Keyword(s):

System Level ◽

High Level Synthesis ◽

Dataflow Graph ◽

High Level

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Thread-Aware Area-Efficient High-Level Synthesis Compiler for Embedded Devices

2021 IEEE/ACM International Symposium on Code Generation and Optimization (CGO) ◽

10.1109/cgo51591.2021.9370341 ◽

2021 ◽

Author(s):

Changsu Kim ◽

Shinnung Jeong ◽

Sungjun Cho ◽

Yongwoo Lee ◽

William Song ◽

...

Keyword(s):

High Level Synthesis ◽

Embedded Devices ◽

High Level ◽

Area Efficient

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Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e92.a.3169 ◽

2009 ◽

Vol E92-A (12) ◽

pp. 3169-3179 ◽

Cited By ~ 7

Author(s):

Akira OHCHI ◽

Nozomu TOGAWA ◽

Masao YANAGISAWA ◽

Tatsuo OHTSUKI

Keyword(s):

High Level Synthesis ◽

High Level

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A Floorplan Aware High-Level Synthesis Algorithm with Body Biasing for Delay Variation Compensation

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e100.a.1439 ◽

2017 ◽

Vol E100.A (7) ◽

pp. 1439-1451

Author(s):

Koki IGAWA ◽

Masao YANAGISAWA ◽

Nozomu TOGAWA

Keyword(s):

High Level Synthesis ◽

Synthesis Algorithm ◽

Body Biasing ◽

High Level ◽

Delay Variation

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Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e97.a.2498 ◽

2014 ◽

Vol E97.A (12) ◽

pp. 2498-2506

Author(s):

Akihiro SUDA ◽

Hideki TAKASE ◽

Kazuyoshi TAKAGI ◽

Naofumi TAKAGI

Keyword(s):

High Level Synthesis ◽

Loop Parallelization ◽

Polyhedral Optimization ◽

High Level ◽

Nested Loop

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A parallel ant colony optimization to globally optimize area in high-level synthesis. (c2011)

10.26756/th.2011.36 ◽

2011 ◽

Author(s):

David Elias Kozhaya

Keyword(s):

Ant Colony Optimization ◽

Ant Colony ◽

High Level Synthesis ◽

High Level

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Language requirements for high-level synthesis

10.3403/00837025 ◽

1996 ◽

Keyword(s):

High Level Synthesis ◽

High Level

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