A Synthesis Algorithm for 4-Bit Reversible Logic Circuits with Minimum Quantum Cost

2014 ◽  
Vol 11 (3) ◽  
pp. 1-19 ◽  
Author(s):  
Zhiqiang Li ◽  
Hanwu Chen ◽  
Xiaoyu Song ◽  
Marek Perkowski
Keyword(s):  
Logic Circuits ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Synthesis Algorithm

scholarly journals Fault Tolerance in Reversible Logic Circuits and Quantum Cost Optimization

2020 ◽  
Vol 39 (5) ◽  
pp. 1099-1116
Author(s):  
Kamaraj Arunachalam ◽  
Marichamy Perumalsamy ◽  
Kaviyashri K. Ponnusamy
Keyword(s):  
Fault Tolerance ◽  
Cost Optimization ◽  
Logic Circuits ◽  
Reversible Logic ◽  
Quantum Cost

Design of Quantum Cost, Garbage Output and Delay Optimized BCD to Excess-3 and 2’s Complement Code Converter

2018 ◽  
Vol 27 (12) ◽  
pp. 1850184 ◽  
Author(s):  
Heranmoy Maity ◽  
Arijit Kumar Barik ◽  
Arindam Biswas ◽  
Anup Kumar Bhattacharjee ◽  
Anita Pal
Keyword(s):  
Logic Gate ◽  
Logic Circuits ◽  
Reversible Logic ◽  
Combinational Logic ◽  
Quantum Cost ◽  
Code Converter ◽  
Garbage Output ◽  
Combinational Logic Circuits ◽  
Logic Functions

In this paper, we have proposed a new reversible logic gate (NG) and also the quantum cost (QC), garbage outputs, delay optimized reversible combinational logic circuits such as four bit 2’s complement code converter circuit, BCD to Excess-3 code converter using reversible logic gate. The proposed NG is used to design a four bit 2’s complement code converter circuit, BCD to Excess-3 code converter and realization of different logic functions such as NOT, AND, NAND, OR, NOR, XOR, NXOR. The proposed (new reversible logic) gate is represented by quantum implementation. The proposed work is verified by Xilinx-ISE simulator software and others logic circuits are also verified. The QC of proposed gate is 5. The QC of four bit 2’s complement code converter and BCD to Excess-3 code converter are 11 and 14 which are better with respect to previous reported results.

Estimation of Power for Reversible Subtractors

2018 ◽  
Vol 7 (4.5) ◽  
pp. 102
Author(s):  
E. V.Naga Lakshmi ◽  
Dr. N.Siva Sankara Reddy
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Logic Gates ◽  
Logic Circuits ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Gate Count ◽  
Garbage Output ◽  
Reversible Logic Gates

In recent years Reversible Logic Circuits (RLC) are proved to be more efficient in terms of power dissipation. Hence, most of the researchers developed Reversible logic circuits for low power applications. RLC are designed with the help of Reversible Logic Gates (RLG).   Efficiency of the Reversible gates is measured in terms of Quantum cost, gate count, garbage output lines, logic depth and constant inputs. In this paper, measurement of power for RLG is done. Basic RLGs are designed using GDI technology and compared in terms of power dissipation. 1 bit Full subtractor is designed using EVNL gate [1] and also with TG& Fy [6] gates. The power dissipation is compared with 1 bit TR gate [5] full subtractor.  Then 2 bit, 4 bit and 8 bit subtractors are designed and compared the powers. Proposed 4 bit and 8 bit full subtractors are dissipating less power when compared to TR gate 4 bit and 8 bit subtractors.  

DESIGN AND OPTIMIZATION OF SINGLE AND MULTIPLE-LOOP REVERSIBLE AND QUANTUM FEEDBACK CIRCUITS

2012 ◽  
Vol 21 (03) ◽  
pp. 1250018 ◽  
Author(s):  
MAJID MOHAMMADI ◽  
ALIAKBAR NIKNAFS ◽  
MOHAMMAD ESHGHI ◽  
GERHARD W. DUECK
Keyword(s):  
Logic Circuits ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Specific Group ◽  
Design And Optimization ◽  
Quantum Feedback ◽  
Synthesis Tool ◽  
Transition Table ◽  
Loop Feedback ◽  
Feedback Circuits

The majority of work in reversible logic circuits has been limited to combinational logic. Researchers are now beginning to suggest designs for sequential circuits. In this paper we propose a new method to design and optimize feedback reversible logic circuits and a specific group of quantum logic circuits based on the reversible state transition table and genetic algorithms (GA). To show the efficiency of the proposed method, some reversible sequential elements such as D and T flip-flops (FFs), with and without clock and reset, and edge triggered FFs are designed. We have also extended our method to multiple loop feedback circuits. The proposed circuits are highly optimized using a GA synthesis tool that allows don't care values. Some of the designs in this paper are presented in other papers; however, the comparisons show that the quantum cost and number of garbage inputs/outputs are reduced efficiently by our method.

A Synthesis Method of Quantum Reversible Logic Circuit Based on Elementary Qutrit Quantum Logic Gates

2015 ◽  
Vol 24 (08) ◽  
pp. 1550121 ◽  
Author(s):  
Fuyou Fan ◽  
Guowu Yang ◽  
Gang Yang ◽  
William N. N. Hung
Keyword(s):  
Quantum Logic ◽  
Synthesis Method ◽  
Logic Gates ◽  
Logic Circuits ◽  
Reversible Logic ◽  
Logic Circuit ◽  
Quantum Gates ◽  
Synthesis Algorithm ◽  
Quantum Logic Gates ◽  
Number Systems

Because ternary computer has more superiority than other d-ary number systems, we focus on the investigation of ternary elementary quantum gates and the synthesis algorithm of ternary quantum logic circuits. Above all, Pauli operators and their matrices on qutrit are introduced. Then eight qutrit operators are selected as elementary operators and eight qutrit quantum logic gates are defined. Permutation groups are introduced to characterize the quantum gates and quantum logic circuits. Some important qutrit quantum logic gates are defined also, such as QNOT, QKCXi, EQKCXi, QSwap, QCNOT and EQCNOT. Based on these elementary gates, we prove two very important theorems: (1) all qutrit quantum reversible logic circuit can be generated by Xi gate and QKCXi gate; (2) all qutrit quantum reversible logic circuits can be generated by Xi gate and QCNOT gate. The two theorems indicate that any complicated qutrit quantum reversible circuit can be constructed by the simplest ternary quantum gate. This will greatly simplify the implementation difficulty of quantum circuit. Subsequently, we propose a synthesis algorithm for qutrit quantum reversible logic circuit, which is verified through simulation experiment by the computer program we have designed.

Realization of a new permutative gate library using controlled-kth-root-of-NOT quantum gates for exact minimization of quantum circuits

2014 ◽  
Vol 12 (05) ◽  
pp. 1450034 ◽  
Author(s):  
Zhiqiang Li ◽  
Xiaoyu Song ◽  
Marek Perkowski ◽  
Hanwu Chen ◽  
Xiaoxia Feng
Keyword(s):  
Quantum Logic ◽  
Logic Gate ◽  
Logic Circuits ◽  
Quantum Circuits ◽  
Quantum Gates ◽  
Quantum Cost ◽  
Efficient Synthesis ◽  
Quantum Logic Gate ◽  
Synthesis Algorithm ◽  
Direct Use

Since non-permutative quantum gates have more complex rules than permutative quantum gates, it is very hard to synthesize quantum logic circuits using non-permutative quantum gates, such as controlled-square-root-of-NOT gates (CV∕CV+ gates). In the efficient synthesis algorithm, direct use of quantum non-permutative gates should be avoided. Rather, the key method is to use quantum gates to create new permutative quantum gates that then replace non-permutative quantum gates. This method assumes the library of quantum gate primitives are constructed so as to have the lowest possible quantum cost. In this paper, we first propose some new CV∕CV+-like gates, i.e. controlled-kth-root-of-NOT gates where k = 2,4,8,…, and give all corresponding matrixes. Further, we also present a novel generic method to quickly and directly construct this new optimal quantum logic gate library using CNOT and these non-permutative quantum gates. Our method introduces new means to find permutative quantum gates with lower quantum cost.

A NOVEL REVERSIBLE ZS GATE AND ITS APPLICATION FOR OPTIMIZATION OF QUANTUM ADDER CIRCUITS

2011 ◽  
Vol 20 (06) ◽  
pp. 1107-1129 ◽  
Author(s):  
RIGUI ZHOU ◽  
YANG SHI ◽  
MANQUN ZHANG ◽  
HUI'AN WANG
Keyword(s):  
Lower Bounds ◽  
Full Adder ◽  
Logic Circuits ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Reversible Gate ◽  
No Wait

The key of optimizing quantum reversible logic lies in automatically constructing quantum reversible logic circuits with the minimal quantum cost. This paper constructs a 4 × 4 reversible gate called ZS gate to build quantum full adder. At the same time, a novel reversible No-Wait-Carry adder (or carry skip adder) by using ZSCGPD based on ZS gate with the least cost is also designed. The adder circuit using the proposed ZSCGPD is much better and optimized than other researchers' counterparts both in terms of garbage outputs, number and kind of reversible gates, and quantum cost. In order to show the efficiency of the proposed designs, lower bounds of the reversible carry skip adder in terms of garbage outputs and quantum cost are proposed as well.

Six Synthesis Methods for Reversible Logic

2007 ◽  
Vol 14 (01) ◽  
pp. 91-116 ◽  
Author(s):  
Yvan Van Rentergem ◽  
Alexis De Vos ◽  
Koen De Keyser
Keyword(s):  
Symmetric Group ◽  
Switch Cost ◽  
Arbitrary Element ◽  
Logic Circuits ◽  
Reversible Logic ◽  
Synthesis Methods ◽  
Quantum Cost ◽  
Coset Space ◽  
Logic Operation ◽  
The Right

The (2w)! reversible transformations on w wires, i.e. reversible logic circuits with w inputs and w outputs, together with the action of cascading, form a group, isomorphic to the symmetric group S2w. Therefore, we investigate the group Sn as well as one of its subgroups isomorphic to Sn/2 × Sn/2. We then consider the left cosets, the right cosets, and the double cosets generated by the subgroup. Each element of a coset can function as the representative of the coset. The coset can then be considered as the set of all group elements that differ from the representative by merely multiplying (either to the left or to the right or to both sides) by an arbitrary element of the subgroup. Different choices of the coset space and different choices of the coset representatives lead to six different syntheses for implementing an arbitrary reversible logic operation into hardware. Evaluation of all six methods, by means of three different cost functions (gate cost, switch cost, and quantum cost), leads to a best choice.

Positive Davio-based synthesis algorithm for reversible logic

2011 ◽  
Author(s):  
Yu Pang ◽  
Shaoquan Wang ◽  
Zhilong He ◽  
Jinzhao Lin ◽  
Sayeeda Sultana ◽  
...  
Keyword(s):  
Reversible Logic ◽  
Synthesis Algorithm
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