Introduction to the TRETS Special Section on the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS'12)

2014 ◽  
Vol 7 (2) ◽  
pp. 1-2
Keyword(s):  
Reconfigurable Computing ◽  
Special Section ◽  
Self Awareness ◽  
Computing Systems

Guest Editorial Special Section on Embedded Reconfigurable Computing Systems

2011 ◽  
Vol 3 (3) ◽  
pp. 75-76
Author(s):  
Fabrizio Ferrandi ◽  
Patrick Lysaght ◽  
Ryan Kastner
Keyword(s):  
Reconfigurable Computing ◽  
Guest Editorial ◽  
Special Section ◽  
Computing Systems

FinFET CMOS logic gates with non-volatile states for reconfigurable computing systems

Integration ◽  
2019 ◽  
Vol 65 ◽  
pp. 97-103 ◽  
Author(s):  
Yu-Fan Chiang ◽  
Wei-Yu Chien ◽  
Yue-Der Chih ◽  
Jonathan Chang ◽  
Chrong Jung Lin ◽  
...  
Keyword(s):  
Reconfigurable Computing ◽  
Logic Gates ◽  
Computing Systems

scholarly journals Application of Multi Layer Artificial Neural Network in the Diagnosis System: A Systematic Review

2018 ◽  
Vol 7 (3) ◽  
pp. 138
Author(s):  
Arvind Singh Rawat ◽  
Arti Rana ◽  
Adesh Kumar ◽  
Ashish Bagwari
Keyword(s):  
Neural Network ◽  
Artificial Neural Network ◽  
Reconfigurable Computing ◽  
Research Papers ◽  
Computing Systems ◽  
System A ◽  
Major Scale ◽  
Artificial Neural ◽  
Artificial Neural Network Ann ◽  
Execution Technique

Basic hardware comprehension of an artificial neural network (ANN), to a major scale depends on the proficientrealization of a distinctneuron. For hardware execution of NNs, mostly FPGA-designed reconfigurable computing systems are favorable .FPGA comprehension of ANNs through a hugeamount of neurons is mainlyan exigentassignment. This workconverses the reviews on various research articles of neural networks whose concernsfocused in execution of more than one input neuron and multilayer with or without linearity property by using FPGA. An execution technique through reserve substitution isprojected to adjust signed decimal facts. A detailed review of many research papers have been done for the <br /> proposed work.

THE PARALLEL-PIPELINED IMPLEMENTATION OF THE FRACTAL IMAGE COMPRESSION FOR RECONFIGURABLE COMPUTING SYSTEMS

2021 ◽  
pp. 37-44
Author(s):  
I. I. Levin ◽  
M. D. Chekina
Keyword(s):  
Image Compression ◽  
Reconfigurable Computing ◽  
Fractal Image Compression ◽  
Computing Systems ◽  
Image Encoding ◽  
Fractal Image ◽  
Computational Structure ◽  
Parallel Pipeline ◽  
Performance Reduction ◽  
Critical Resource

The developed fractal image compression method, implemented for reconfigurable computing systems is described. The main idea parallel fractal image compression based on parallel execution pairwise comparison of domain and rank blocks. Achievement high performance occurs at the expense of simultaneously comparing maximum number of pairs. Implementation fractal image compression for reconfigurable computing systems has two critical resources, as number of input channels and FPGA Look-up Table (LUT). The main critical resource for fractal image compression is data channels, and implementation this task for reconfigurable computing systems requires parallel-pipeline computations organization replace parallel, preliminarily produced performance reduction parallel computational structure. The main critical resource for fractal image compression is data channels, and implementation this task for reconfigurable computing systems requires parallel-pipeline computations organization replace parallel computations organiation. For using parallel-pipeline computations organization, preliminarily have produce performance reduction parallel computational structure. Each operator has routed to computational structure sequentially (bit by bit) to save computational resources and reduces equipment downtime. Storing iterated functions system coefficients for image encoding has been introduced in data structure, which correlates between corresponding parameters the numbers of rank and domain blocks. Applying this approach for parallel-pipeline programs allows scaling computing structure to plurality programmable logic arrays (FPGAs). Task implementation on the reconfigurable computer system Tertius-2 containing eight FPGAs 15 000 times provides performed acceleration relatively with universal multi-core processor, and 18 – 25 times whit to existing solutions for FPGAs.

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