Author retrospective improving data cache performance by pre-executing instructions under a cache miss

2014 ◽  
Author(s):  
Trevor Mudge
Keyword(s):  
Data Cache ◽  
Cache Performance ◽  
Cache Miss

Design of an Intelligent Data Cache with Replacement Policy

2019 ◽  
Vol 10 (2) ◽  
pp. 87-107
Author(s):  
B. Shameedha Begum ◽  
N. Ramasubramanian
Keyword(s):  
Real Time ◽  
Replacement Policy ◽  
Data Cache ◽  
Cache Performance ◽  
Performance Requirements ◽  
Novel Approach ◽  
Reconfigurable Caches ◽  
Real Time Applications ◽  
Hard Real Time ◽  
Replacement Algorithms

Embedded systems are designed for a variety of applications ranging from Hard Real Time applications to mobile computing, which demands various types of cache designs for better performance. Since real-time applications place stringent requirements on performance, the role of the cache subsystem assumes significance. Reconfigurable caches meet performance requirements under this context. Existing reconfigurable caches tend to use associativity and size for maximizing cache performance. This article proposes a novel approach of a reconfigurable and intelligent data cache (L1) based on replacement algorithms. An intelligent embedded data cache and a dynamic reconfigurable intelligent embedded data cache have been implemented using Verilog 2001 and tested for cache performance. Data collected by enabling the cache with two different replacement strategies have shown that the hit rate improves by 40% when compared to LRU and 21% when compared to MRU for sequential applications which will significantly improve performance of embedded real time application.

Improving data cache performance with integrated use of split caches, victim cache and stream buffers

2005 ◽  
Vol 33 (3) ◽  
pp. 41-48 ◽  
Author(s):  
Afrin Naz ◽  
Mehran Rezaei ◽  
Krishna Kavi ◽  
Philip Sweany
Keyword(s):  
Data Cache ◽  
Cache Performance

A SPLIT L2 DATA CACHE FOR SCALABLE CC-NUMA MULTIPROCESSORS

2005 ◽  
Vol 14 (03) ◽  
pp. 605-617 ◽  
Author(s):  
SUNG WOO CHUNG ◽  
HYONG-SHIK KIM ◽  
CHU SHIK JHON
Keyword(s):  
Execution Time ◽  
Memory Access ◽  
Remote Memory ◽  
Access Time ◽  
Data Cache ◽  
Total Execution Time ◽  
Memory Address ◽  
L2 Cache ◽  
Cache Miss

In scalable CC-NUMA multiprocessors, it is crucial to reduce the average memory access time. For applications where the second-level (L2) cache is large enough, we propose a split L2 cache to utilize the surplus space. The split L2 cache is composed of a traditional LRU cache and an RVC (Remote Victim Cache) which only stores the data of remote memory address range. Thus, it reduces the average L2 cache miss time by keeping remote blocks that would be discarded otherwise. Though the split cache does not reduce the miss rates, it is observed to reduce the total execution time effectively by up to 27%.It even outperform an LRU cache of double size.

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