Invasive Tightly-Coupled Processor Arrays

2014 ◽  
Vol 13 (4s) ◽  
pp. 1-29 ◽  
Author(s):  
Frank Hannig ◽  
Vahid Lari ◽  
Srinivas Boppu ◽  
Alexandru Tanase ◽  
Oliver Reiche
Keyword(s):  
Processor Arrays ◽  
Tightly Coupled

Hierarchical power management for adaptive tightly-coupled processor arrays

2013 ◽  
Vol 18 (1) ◽  
pp. 1-25 ◽  
Author(s):  
Vahid Lari ◽  
Shravan Muddasani ◽  
Srinivas Boppu ◽  
Frank Hannig ◽  
Moritz Schmid ◽  
...  
Keyword(s):  
Power Management ◽  
Processor Arrays ◽  
Tightly Coupled ◽  
Hierarchical Power Management

Hand Sign Recognition via Deep Learning on Tightly Coupled Processor Arrays

2021 ◽  
Author(s):  
Christian Heidorn ◽  
Dominik Walter ◽  
Yunus Emre Candir ◽  
Frank Hannig ◽  
Jurgen Teich
Keyword(s):  
Deep Learning ◽  
Sign Recognition ◽  
Processor Arrays ◽  
Tightly Coupled

scholarly journals Safe Overclocking of Tightly Coupled CGRAs and Processor Arrays using Razor

2013 ◽  
Author(s):  
Alexander Brant ◽  
Ameer Abdelhadi ◽  
Douglas H. H. Sim ◽  
Shao Lin Tang ◽  
Michael Xi Yue ◽  
...  
Keyword(s):  
Processor Arrays ◽  
Tightly Coupled

Acceleration of Optical Flow Computations on Tightly-Coupled Processor Arrays

2013 ◽  
Vol 30 (1) ◽  
pp. 80-89 ◽  
Author(s):  
Éricles Rodrigues Sousa ◽  
Alexandru Tanase ◽  
Vahid Lari ◽  
Frank Hannig ◽  
Jürgen Teich ◽  
...  
Keyword(s):  
Optical Flow ◽  
Processor Arrays ◽  
Tightly Coupled

scholarly journals Temperature modeling and emulation of an ASIC temperature monitor system for Tightly-Coupled Processor Arrays (TCPAs)

2014 ◽  
Vol 12 ◽  
pp. 103-109 ◽  
Author(s):  
E. Glocker ◽  
S. Boppu ◽  
Q. Chen ◽  
U. Schlichtmann ◽  
J. Teich ◽  
...  
Keyword(s):  
Monitoring System ◽  
Temperature Monitoring ◽  
Monitor System ◽  
Processor Array ◽  
Modeling Approach ◽  
Temperature Modeling ◽  
Processor Arrays ◽  
Tightly Coupled ◽  
Temperature Monitor ◽  
Run Time

Abstract. This contribution provides an approach for emulating the behaviour of an ASIC temperature monitoring system (TMon) during run-time for a tightly-coupled processor array (TCPA) of a heterogeneous invasive multi-tile architecture to be used for FPGA prototyping. It is based on a thermal RC modeling approach. Also different usage scenarios of TCPA are analyzed and compared.

Compact Code Generation for Tightly-Coupled Processor Arrays

2014 ◽  
Vol 77 (1-2) ◽  
pp. 5-29 ◽  
Author(s):  
Srinivas Boppu ◽  
Frank Hannig ◽  
Jürgen Teich
Keyword(s):  
Code Generation ◽  
Processor Arrays ◽  
Tightly Coupled

scholarly journals Symbolic Loop Compilation for Tightly Coupled Processor Arrays

2021 ◽  
Vol 20 (5) ◽  
pp. 1-31
Author(s):  
Michael Witterauf ◽  
Dominik Walter ◽  
Frank Hannig ◽  
Jürgen Teich
Keyword(s):  
Matrix Multiplication ◽  
Processor Array ◽  
Problem Size ◽  
Modulo Scheduling ◽  
Processor Arrays ◽  
Complete Problems ◽  
Tightly Coupled ◽  
Np Complete ◽  
Configuration Data ◽  
Improved Performance

Tightly Coupled Processor Arrays (TCPAs), a class of massively parallel loop accelerators, allow applications to offload computationally expensive loops for improved performance and energy efficiency. To achieve these two goals, executing a loop on a TCPA requires an efficient generation of specific programs as well as other configuration data for each distinct combination of loop bounds and number of available processing elements (PEs). Since both these parameters are generally unknown at compile time—the number of available PEs due to dynamic resource management, and the loop bounds, because they depend on the problem size—both the programs and configuration data must be generated at runtime. However, pure just-in-time compilation is impractical, because mapping a loop program onto a TCPA entails solving multiple NP-complete problems. As a solution, this article proposes a unique mixed static/dynamic approach called symbolic loop compilation. It is shown that at compile time, the NP-complete problems (modulo scheduling, register allocation, and routing) can still be solved to optimality in a symbolic way resulting in a so-called symbolic configuration , a space-efficient intermediate representation parameterized in the loop bounds and number of PEs. This phase is called symbolic mapping . At runtime, for each requested accelerated execution of a loop program with given loop bounds and known number of available PEs, a concrete configuration , including PE programs and configuration data for all other components, is generated from the symbolic configuration according to these parameter values. This phase is called instantiation . We describe both phases in detail and show that instantiation runs in polynomial time with its most complex step, program instantiation, not directly depending on the number of PEs and thus scaling to arbitrary sizes of TCPAs. To validate the efficiency of this mixed static/dynamic compilation approach, we apply symbolic loop compilation to a set of real-world loop programs from several domains, measuring both compilation time and space requirements. Our experiments confirm that a symbolic configuration is a space-efficient representation suited for systems with little memory—in many cases, a symbolic configuration is smaller than even a single concrete configuration instantiated from it—and that the times for the runtime phase of program instantiation and configuration loading are negligible and moreover independent of the size of the available processor array. To give an example, instantiating a configuration for a matrix-matrix multiplication benchmark takes equally long for 4× 4 and 32× 32 PEs.

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