Critical-path-aware high-level synthesis with distributed controller for fast timing closure

2014 ◽  
Vol 19 (2) ◽  
pp. 1-29 ◽  
Author(s):  
Seokhyun Lee ◽  
Kiyoung Choi
Keyword(s):  
Critical Path ◽  
High Level Synthesis ◽  
Timing Closure ◽  
Fast Timing ◽  
Distributed Controller ◽  
High Level

scholarly journals Design of Synthesizable, Retimed Digital Filters Using FPGA Based Path Solvers with MCM Approach: Comparison and CAD Tool

VLSI Design ◽  
2014 ◽  
Vol 2014 ◽  
pp. 1-18 ◽  
Author(s):  
Deepa Yagain ◽  
A. Vijaya Krishna
Keyword(s):  
Digital Filter ◽  
Computer Aided Design ◽  
Performance Metrics ◽  
Filter Design ◽  
Critical Path ◽  
Computation Time ◽  
Design Tool ◽  
High Level Synthesis ◽  
Clock Frequency ◽  
High Level

Retiming is a transformation which can be applied to digital filter blocks that can increase the clock frequency. This transformation requires computation of critical path and shortest path at various stages. In literature, this problem is addressed at multiple points. However, very little attention is given to path solver blocks in retiming transformation algorithm which takes up most of the computation time. In this paper, we address the problem of optimizing the speed of path solvers in retiming transformation by introducing high level synthesis of path solver algorithm architectures on FPGA and a computer aided design tool. Filters have their combination blocks as adders, multipliers, and delay elements. Avoiding costly multipliers is very much needed for filter hardware implementation. This can be achieved efficiently by using multiplierless MCM technique. In the present work, retiming which is a high level synthesis optimization method is combined with multiplierless filter implementations using MCM algorithm. It is seen that retiming multiplierless designs gives better performance in terms of operating frequency. This paper also compares various retiming techniques for multiplierless digital filter design with respect to VLSI performance metrics such as area, speed, and power.

A Distributed Controller for Managing Speculative Functional Units in High Level Synthesis

2011 ◽  
Vol 30 (3) ◽  
pp. 350-363 ◽  
Author(s):  
Alberto A. Del Barrio ◽  
Seda Ogrenci Memik ◽  
María C. Molina ◽  
José M. Mendias ◽  
Román Hermida
Keyword(s):  
High Level Synthesis ◽  
Distributed Controller ◽  
Functional Units ◽  
High Level

Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures

2009 ◽  
Vol E92-A (12) ◽  
pp. 3169-3179 ◽  
Author(s):  
Akira OHCHI ◽  
Nozomu TOGAWA ◽  
Masao YANAGISAWA ◽  
Tatsuo OHTSUKI
Keyword(s):  
High Level Synthesis ◽  
High Level
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