An asymmetric dual-processor architecture for low-power information appliances

François Guimbretiére; Shenwei Liu; Han Wang; Rajit Manohar

doi:10.1145/2560538

An asymmetric dual-processor architecture for low-power information appliances

ACM Transactions on Embedded Computing Systems ◽

10.1145/2560538 ◽

2014 ◽

Vol 13 (4) ◽

pp. 1-19 ◽

Cited By ~ 4

Author(s):

François Guimbretiére ◽

Shenwei Liu ◽

Han Wang ◽

Rajit Manohar

Keyword(s):

Low Power ◽

Processor Architecture ◽

Information Appliances

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Low power sensor node processor architecture

2010 17th IEEE International Conference on Electronics, Circuits and Systems ◽

10.1109/icecs.2010.5724661 ◽

2010 ◽

Cited By ~ 3

Author(s):

Goran Panic ◽

Thomas Basmer ◽

Klaus Tittelbach-Helmrich ◽

Lukasz Lopacinski

Keyword(s):

Low Power ◽

Sensor Node ◽

Processor Architecture ◽

Power Sensor

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A delay spread based low power reconfigurable FFT processor architecture for wireless receiver

Proceedings 2003 International Symposium on System-on-Chip ◽

10.1109/issoc.2003.1267736 ◽

2004 ◽

Cited By ~ 12

Author(s):

M. Hasan ◽

T. Arslan ◽

J.S. Thompson

Keyword(s):

Low Power ◽

Delay Spread ◽

Processor Architecture ◽

Wireless Receiver ◽

Fft Processor

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A low area and low power programmable baseband processor architecture

Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05) ◽

10.1109/iwsoc.2005.14 ◽

2005 ◽

Cited By ~ 7

Author(s):

E. Tell ◽

A. Nilsson ◽

D. Liu

Keyword(s):

Low Power ◽

Processor Architecture ◽

Low Area ◽

Baseband Processor

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Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer

Proceedings of 1996 International Symposium on Low Power Electronics and Design ◽

10.1109/lpe.1996.547538 ◽

2002 ◽

Cited By ~ 11

Author(s):

M. Hiraki ◽

R.S. Bajwa ◽

H. Kojima ◽

D.J. Gorny ◽

K. Nitta ◽

...

Keyword(s):

Low Power ◽

Processor Architecture

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Low-power processor architecture exploration for online biomedical signal analysis

IET Circuits Devices & Systems ◽

10.1049/iet-cds.2012.0011 ◽

2012 ◽

Vol 6 (5) ◽

pp. 279 ◽

Cited By ~ 10

Author(s):

A.Y. Dogan ◽

J. Constantin ◽

D. Atienza ◽

A. Burg ◽

L. Benini

Keyword(s):

Low Power ◽

Signal Analysis ◽

Processor Architecture ◽

Biomedical Signal ◽

Biomedical Signal Analysis ◽

Architecture Exploration

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A LOW-POWER WIRELESS DISTRIBUTED DYNAMIC NETWORK DESIGN CONCEPT: FFT PROCESSOR ARCHITECTURE

Communications ◽

10.2316/journal.214.2012.1.214-1025 ◽

2012 ◽

Vol 1 (1) ◽

Cited By ~ 1

Author(s):

Vyasa Sai ◽

Ajay Ogirala ◽

Marlin H. Mickle

Keyword(s):

Low Power ◽

Network Design ◽

Dynamic Network ◽

Design Concept ◽

Processor Architecture ◽

Fft Processor ◽

Dynamic Network Design

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An Ultra-low-power Processor Architecture For High-performance Computing And Other Compute-intensive Applications

10.5339/qfarc.2014.itpp0503 ◽

2014 ◽

Author(s):

Toshikazu Ebisuzaki ◽

Junichiro Makino

Keyword(s):

Low Power ◽

High Performance Computing ◽

High Performance ◽

Processor Architecture ◽

Ultra Low Power ◽

Performance Computing

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Low-Power Digital Signal Processor Architecture for Wireless Sensor Nodes

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2013.2238645 ◽

2014 ◽

Vol 22 (2) ◽

pp. 313-321 ◽

Cited By ~ 15

Author(s):

Cedric Walravens ◽

Wim Dehaene

Keyword(s):

Low Power ◽

Digital Signal Processor ◽

Digital Signal ◽

Sensor Nodes ◽

Wireless Sensor ◽

Processor Architecture ◽

Wireless Sensor Nodes ◽

Signal Processor

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Low Power Digital Signal Processor Architecture For Wireless Sensor Nodes By Using Parallel Prefix Technique

IOSR Journal of Electrical and Electronics Engineering ◽

10.9790/1676-09125659 ◽

2014 ◽

Vol 9 (1) ◽

pp. 56-59

Author(s):

S.Anisha Jenifer ◽

◽

J.H. Ajin

Keyword(s):

Low Power ◽

Digital Signal Processor ◽

Digital Signal ◽

Sensor Nodes ◽

Wireless Sensor ◽

Processor Architecture ◽

Wireless Sensor Nodes ◽

Parallel Prefix ◽

Signal Processor

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Low Power R4SDC Pipelined FFT Processor Architecture

IOSR Journal of VLSI and Signal processing ◽

10.9790/4200-0166875 ◽

2013 ◽

Vol 1 (6) ◽

pp. 68-75

Author(s):

Anjana R Anjana R

Keyword(s):

Low Power ◽

Processor Architecture ◽

Fft Processor

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