A survey of optimization techniques targeting low power VLSI circuits

1995 ◽  
Author(s):  
Srinivas Devadas ◽  
Sharad Malik
Keyword(s):  
Low Power ◽  
Vlsi Circuits ◽  
Optimization Techniques

scholarly journals Low Power VLSI Design Techniques: A Review

2021 ◽  
Vol 23 (11) ◽  
pp. 172-183
Author(s):  
Ketan J. Raut ◽  
◽  
Abhijit V. Chitre ◽  
Minal S. Deshmukh ◽  
Kiran Magar ◽  
...  
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Vlsi Design ◽  
Cmos Technology ◽  
Vlsi Circuits ◽  
Optimization Techniques ◽  
Battery Life ◽  
Dynamic Power ◽  
Cmos Vlsi

Since CMOS technology consumes less power it is a key technology for VLSI circuit design. With technologies reaching the scale of 10 nm, static and dynamic power dissipation in CMOS VLSI circuits are major issues. Dynamic power dissipation is increased due to requirement of high speed and static power dissipation is at much higher side now a days even compared to dynamic power dissipation due to very high gate leakage current and subthreshold leakage. Low power consumption is equally important as speed in many applications since it leads to a reduction in the package cost and extended battery life. This paper surveys contemporary optimization techniques that aims low power dissipation in VLSI circuits.

scholarly journals A Low Power AC/DC Interface for Wind-Powered Sensor Nodes

Energies ◽  
2021 ◽  
Vol 14 (7) ◽  
pp. 1823
Author(s):  
Mohammad Haidar ◽  
Hussein Chible ◽  
Corrado Boragno ◽  
Daniele D. Caviglia
Keyword(s):  
Low Power ◽  
Power Supply ◽  
Energy Harvester ◽  
Optimization Techniques ◽  
Sensor Nodes ◽  
Wireless Sensor ◽  
Constant Voltage ◽  
Interface Circuit ◽  
Switching Converter ◽  
Input Signals

Sensor nodes have been assigned a lot of tasks in a connected environment that is growing rapidly. The power supply remains a challenge that is not answered convincingly. Energy harvesting is an emerging solution that is being studied to integrate in low power applications such as internet of things (IoT) and wireless sensor networks (WSN). In this work an interface circuit for a novel fluttering wind energy harvester is presented. The system consists of a switching converter controlled by a low power microcontroller. Optimization techniques on the hardware and software level have been implemented, and a prototype is developed for testing. Experiments have been done with generated input signals resulting in up to 67% efficiency for a constant voltage input. Other experiments were conducted in a wind tunnel that showed a transient output that is compatible with the target applications.

scholarly journals Analysis On Power Gating Circuits Based Low Power VLSI Circuits (BCD Adder)

2021 ◽  
Vol 2089 (1) ◽  
pp. 012080
Author(s):  
M. Srinivas ◽  
K.V. Daya Sagar
Keyword(s):  
Energy Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Leakage Power ◽  
Vlsi Circuits ◽  
Battery Life

Abstract Currently, energy consumption in the digital circuit is a key design parameter for emerging mobile products. The principal cause of the power dissipation during idle mode is leakage currents, which are rising dramatically. Sub-threshold leakage is increased by the scaling of threshold voltage when gate current leakage increases because oxide thickness is scaled. With rising demands for mobile devices, leakage energy consumption has received even greater attention. Since a mobile device spends most of its time in standby mode, leakage power savings need to prolong the battery life. That is why low power has become a significant factor in CMOS circuit design. The required design and simulation of an AND gate with the BSIM4 MOS parameter model at 27 0C, supply voltage of 0,70V with CMOS technology of 65nm are the validation of the suitability of the proposed circuit technology. AND simulation. The performance parameters for the two AND input gate are compared with the current MTCMOS and SCCMOS techniques, such as sub-threshold leakage power dissipations in active and standby modes, the dynamic dissipation, and propagation period. The proposed hybrid super cutoff complete stack technique compared to the current MTCMOS technology shows a reduction in sub-threshold dissipation power dissipation by 3. 50x and 1.15x in standby modes and active modes respectively. The hybrid surface-cutting technique also shows savings of 2,50 and 1,04 in power dissipation at the sub-threshold in standby modes and active modes compared with the existing SCCMOS Technique.

An efficient and reliable MRF-based methodology for designing low-power VLSI circuits

Integration ◽  
2020 ◽  
Vol 73 ◽  
pp. 77-88 ◽  
Author(s):  
Sayyed Mohammad Razavi ◽  
Seyyed Mohammad Razavi
Keyword(s):  
Low Power ◽  
Vlsi Circuits

scholarly journals Encoding Schemes for Reducing Transition Activity and Power Consumption in VLSI Interconnects-A Review

2018 ◽  
Vol 7 (3.1) ◽  
pp. 34
Author(s):  
Vithyalakshmi. N ◽  
Nagarajan P ◽  
Ashok Kumar.N ◽  
Vinoth. G.S
Keyword(s):  
Energy Dissipation ◽  
Power Consumption ◽  
Low Power ◽  
Vlsi Design ◽  
Low Power Design ◽  
System Size ◽  
Vlsi Circuits ◽  
Portable Devices ◽  
Dynamic Power ◽  
Transition Activity

Low power design is a foremost challenging issue in recent applications like mobile phones and portable devices. Advances in VLSI technology have enabled the realization of complicated circuits in single chip, reducing system size and power utilization. In low power VLSI design energy dissipation has to be more significant. So to minimize the power consumption of circuits various power components and their effects must be identified. Dynamic power is the major energy dissipation in micro power circuits. Bus transition activity is the major source of dynamic power consumption in low power VLSI circuits. The dynamic power of any complex circuits cannot be estimated by the simple calculations. Therefore this paper review different encoding schemes for reduction of transition activity and power dissipation. 

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