An integrated general purpose automated test environment

1993 ◽  
Author(s):  
Peter A. Vogel
Keyword(s):  
General Purpose ◽  
Test Environment ◽  
Automated Test

scholarly journals A Unique Test Bench for Various System-on-a-Chip

2017 ◽  
Vol 7 (6) ◽  
pp. 3318 ◽  
Author(s):  
Sridevi Chitti ◽  
P. Chandrasekhar ◽  
M. Asharani
Keyword(s):  
Intellectual Property ◽  
Test Bench ◽  
General Purpose ◽  
Technology Tools ◽  
Automated Test ◽  
System On A Chip ◽  
Verification Process ◽  
Verification Methodology ◽  
Efficient Verification ◽  
State Of Art

This paper discusses a standard flow on how an automated test bench environment which is randomized with constraints can verify a SOC efficiently for its functionality and coverage. Today, in the time of multimillion gate ASICs, reusable intellectual property (IP), and system-on-a-chip (SoC) designs, verification consumes about 70 % of the design effort. Automation means a machine completes a task autonomously, quicker and with predictable results. Automation requires standard processes with well-defined inputs and outputs. By using this efficient methodology it is possible to provide a general purpose automation solution for verification, given today’s technology. Tools automating various portions of the verification process are being introduced. Here, we have Communication based SOC The content of the paper discusses about the methodology used to verify such a SOC-based environment. Cadence Efficient Verification Methodology libraries are explored for the solution of this problem. We can take this as a state of art approach in verifying SOC environments. The goal of this paper is to emphasize the unique testbench for different SOC using Efficient Verification Constructs implemented in system verilog for SOC verification.

scholarly journals Automated Test System for Test and Evaluation of C-Band Transmitter Packages for Geosat Spacecrafts

2019 ◽  
Vol 8 (2) ◽  
pp. 4591-4596
Keyword(s):  
Rapid Development ◽  
User Interaction ◽  
Test System ◽  
General Purpose ◽  
Virtual Instrumentation ◽  
Labview Software ◽  
Test And Evaluation ◽  
Automated Test System ◽  
Automated Test ◽  
Component Interface

The aim of this paper is to develop an Automated Test System (ATS) for the Test and Evaluation of C-Band Transmitter packages for GEOSAT Space crafts using Virtual Instrumentation. Efficiency, coverage, quality and accuracy for the test and evaluation of Device Under Test (DUT) can be increased by Automated Testing. Minimizing the errors anticipated with manual intervention. Automated Test System using Virtual instrumentation (VI) combines rapid development software and modular, flexible hardware to create user-defined test systems. Here Modular PXI (Peripheral component interface Extensions for Instrumentation) instruments from National Instruments are used with NI-LabVIEW software for realizing the ATS. For characterizing the C-Band Transmitter, Spectrum analyzer & Digital Multimeter (DMM) is configured in PXI form-factor and the Power supply is controlled through GPIB (General Purpose Interface Bus) bus. The complete software is developed using NI LabVIEW which takes care of configuring the test condition and analyzing the DUT performance. The user friendly GUI well takes care of user interaction to the ATS.

scholarly journals Automated test generation for optimizing compilers with OpenMP support

2018 ◽  
Vol 210 ◽  
pp. 04014
Author(s):  
Svyatoslav Pankratov
Keyword(s):  
Test Generation ◽  
Parallel Computations ◽  
General Purpose ◽  
Optimizing Compilers ◽  
Correct Operation ◽  
Automated Test Generation ◽  
Important Stage ◽  
Automated Test ◽  
Automate Test

The correctness of the compiler is a necessary requirement for the correct operation of the software compiled by it. Therefore, the most important stage in the development of the compiler is verification. Recent widespread of multi-core processors and graphics core integrated to CPU emphasized the problem of the transition from single-threaded to multi-threaded computing and re-usage of graphics core for general purpose heterogeneous parallel computations in particular. In this paper, we are presenting an approach to automate test creation for the verification of the compiler with OpenMP support, based on a generator that uses grammars to generate syntactically correct executable tests.

scholarly journals An Automated Testing Method for PXI Chassis Software Driver

2019 ◽  
Vol 8 (11) ◽  
pp. 4064-4071
Keyword(s):  
Software Testing ◽  
Current Trend ◽  
Software Tool ◽  
Test System ◽  
Test Duration ◽  
Test Environment ◽  
Test Configuration ◽  
Testing Environment ◽  
Automated Test ◽  
Automated Software

PCI extensions for instrumentation (PXI) chassis is a multi-vendor interoperable device. It can interconnect with many chassis, module and computers. To make sure a device driver is able to function in a specific configuration, it must go through a series of tests. The complexity of PXI software testing has increased when it needs to cover multiple configurations for a single driver. Majority of the automated test systems will execute tests without having the mechanism to verify the test environment. To improve the PXI chassis driver test duration, the current trend of automated software testing only executes a single test configuration. Thus, an automated test software with the capability to execute multi-test configuration is required. In order to develop this tool, a server-client concept is adopted. The advantage of server-client is to centralize the testing when multiple tests are performed. The software tool client will start once it is booted into the operating system; the test system will connect to server and wait for further action from server. When server detects incoming client connection, it will automatically verify and fix the testing environment; if the client fulfills the test suite requirement it will start to execute the test system. All client test summary results will be updated to the server. The results show an average of 17.1% test duration reduction on the planned test configuration when the automated software tool is applied on testing. Besides, the results indicate higher controller hardware performance can reduce the test duration.

Correlation between dislocation, grain boundary and interface of duplex SS in stress corrosion cracking(SCC)

1990 ◽  
Vol 48 (4) ◽  
pp. 928-929
Author(s):  
Wang Zheng-fang ◽  
Z.F. Wang
Keyword(s):  
Stainless Steel ◽  
Thermal Cycle ◽  
Secondary Phase ◽  
Corrosion Cracking ◽  
Coarse Grained ◽  
Test Environment ◽  
Fine Grained ◽  
Evaluation Test ◽  
Welding Thermal Cycle ◽  
Micro Analysis

The main purpose of this study highlights on the evaluation of chloride SCC resistance of the material,duplex stainless steel,OOCr18Ni5Mo3Si2 (18-5Mo) and its welded coarse grained zone(CGZ).18-5Mo is a dual phases (A+F) stainless steel with yield strength:512N/mm2 .The proportion of secondary Phase(A phase) accounts for 30-35% of the total with fine grained and homogeneously distributed A and F phases(Fig.1).After being welded by a specific welding thermal cycle to the material,i.e. Tmax=1350°C and t8/5=20s,microstructure may change from fine grained morphology to coarse grained morphology and from homogeneously distributed of A phase to a concentration of A phase(Fig.2).Meanwhile,the proportion of A phase reduced from 35% to 5-10°o.For this reason it is known as welded coarse grained zone(CGZ).In association with difference of microstructure between base metal and welded CGZ,so chloride SCC resistance also differ from each other.Test procedures:Constant load tensile test(CLTT) were performed for recording Esce-t curve by which corrosion cracking growth can be described, tf,fractured time,can also be recorded by the test which is taken as a electrochemical behavior and mechanical property for SCC resistance evaluation. Test environment:143°C boiling 42%MgCl2 solution is used.Besides, micro analysis were conducted with light microscopy(LM),SEM,TEM,and Auger energy spectrum(AES) so as to reveal the correlation between the data generated by the CLTT results and micro analysis.

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