Highly configurable transaction management for embedded systems

2007 ◽  
Author(s):  
Mario Pukall ◽  
Thomas Leich ◽  
Martin Kuhlemann ◽  
Marko Rosenmueller
Keyword(s):  
Embedded Systems ◽  
Transaction Management

Discontinuous Institutional Alternatives in the Context of Economy Deregulation

2004 ◽  
pp. 94-110 ◽  
Author(s):  
A. Shastitko
Keyword(s):  
Market Failure ◽  
Transaction Management ◽  
Market Failures ◽  
Relative Cost ◽  
State Participation

Various ways of state participation in the mechanisms of transaction management are considered in the article. Differences between compensation and elimination of the market failures are identified. Opportunities and risks of non-regulatory alternatives usage as a mean of market failure compensation are described. Based on classification of goods correlated to relative cost of their useful characteristics evaluation (search, experience, merit) questions of institutional alternatives in three areas (political, financial and commodity) are examined.

Development of embedded systems to control toxic compounds in textile industries

2012 ◽  
Vol 1 (5) ◽  
pp. 115-117
Author(s):  
Jahnavi KRM Jahnavi KRM ◽  
◽  
Raghavendra Rao K ◽  
Padma Suvarna R
Keyword(s):  
Embedded Systems ◽  
Toxic Compounds ◽  
Textile Industries

Proposal and Evaluation of Mutual Exclusion Method using Lock-free Algorism for Embedded Systems using Multi-core Processor

2019 ◽  
Vol 139 (7) ◽  
pp. 802-811
Author(s):  
Kenta Fujimoto ◽  
Shingo Oidate ◽  
Yuhei Yabuta ◽  
Atsuyuki Takahashi ◽  
Takuya Yamasaki ◽  
...  
Keyword(s):  
Embedded Systems ◽  
Mutual Exclusion ◽  
Exclusion Method ◽  
Multi Core Processor

Towards Okinawa-style Robot-embedded Systems

2013 ◽  
Vol 133 (2) ◽  
pp. 111-115 ◽  
Author(s):  
Takashi Anezaki ◽  
Suriyon Tansuriyavong ◽  
Chikatoshi Yamada
Keyword(s):  
Embedded Systems

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

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