Adaptive reorder buffers for SMT processors

Proceedings of the 15th international conference on Parallel architectures and compilation techniques - PACT '06 ◽

10.1145/1152154.1152192 ◽

2006 ◽

Cited By ~ 11

Author(s):

Joseph Sharkey ◽

Deniz Balkan ◽

Dmitry Ponomarev

Keyword(s):

Reorder Buffers

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Enlarging Instruction Window through Separated Reorder Buffers for High Performance Computing

Communications in Computer and Information Science - Future Information Technology ◽

10.1007/978-3-642-22333-4_21 ◽

2011 ◽

pp. 183-189

Author(s):

Min Choi ◽

Jonghyuk Park ◽

Young-Sik Jeong

Keyword(s):

High Performance Computing ◽

High Performance ◽

Reorder Buffers ◽

Performance Computing

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Two-Level Reorder Buffers: Accelerating Memory-Bound Applications on SMT Architectures

10.1109/icpp.2008.24 ◽

2008 ◽

Author(s):

Jason Loew ◽

Dmitry Ponomarev

Keyword(s):

Reorder Buffers

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Checkpoint processing and recovery: an efficient, scalable alternative to reorder buffers

IEEE Micro ◽

10.1109/mm.2003.1261382 ◽

2003 ◽

Vol 23 (6) ◽

pp. 11-19 ◽

Cited By ~ 6

Author(s):

H. Akkary ◽

R. Rajwar ◽

S.T. Srinivasan

Keyword(s):

Reorder Buffers

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An Adaptive Technique for Reducing Leakage and Dynamic Power in Register Files and Reorder Buffers

Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation ◽

10.1007/11556930_51 ◽

2005 ◽

pp. 498-507 ◽

Cited By ~ 2

Author(s):

Shadi T. Khasawneh ◽

Kanad Ghose

Keyword(s):

Dynamic Power ◽

Adaptive Technique ◽

Reorder Buffers

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