The cache performance and optimizations of blocked algorithms

Proceedings of the fourth international conference on Architectural support for programming languages and operating systems - ASPLOS-IV ◽

10.1145/106972.106981 ◽

1991 ◽

Cited By ~ 393

Author(s):

Monica D. Lam ◽

Edward E. Rothberg ◽

Michael E. Wolf

Keyword(s):

Cache Performance ◽

Blocked Algorithms

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The cache performance and optimizations of blocked algorithms

ACM SIGARCH Computer Architecture News ◽

10.1145/106975.106981 ◽

1991 ◽

Vol 19 (2) ◽

pp. 63-74 ◽

Cited By ~ 18

Author(s):

Monica D. Lam ◽

Edward E. Rothberg ◽

Michael E. Wolf

Keyword(s):

Cache Performance ◽

Blocked Algorithms

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The cache performance and optimizations of blocked algorithms

ACM SIGOPS Operating Systems Review ◽

10.1145/106974.106981 ◽

1991 ◽

Vol 25 (Special Issue) ◽

pp. 63-74 ◽

Cited By ~ 19

Author(s):

Monica D. Lam ◽

Edward E. Rothberg ◽

Michael E. Wolf

Keyword(s):

Cache Performance ◽

Blocked Algorithms

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The cache performance and optimizations of blocked algorithms

ACM SIGPLAN Notices ◽

10.1145/106973.106981 ◽

1991 ◽

Vol 26 (4) ◽

pp. 63-74 ◽

Cited By ~ 22

Author(s):

Monica D. Lam ◽

Edward E. Rothberg ◽

Michael E. Wolf

Keyword(s):

Cache Performance ◽

Blocked Algorithms

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On the effects of content compression on Web cache performance

Proceedings ITCC 2003. International Conference on Information Technology: Coding and Computing ◽

10.1109/itcc.2003.1197573 ◽

2004 ◽

Cited By ~ 1

Author(s):

S. Ahuja ◽

Tao Wu ◽

S. Dixit

Keyword(s):

Cache Performance ◽

Web Cache

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WRP: Weighting Replacement Policy to Improve Cache Performance

International Symposium on Computer Science and its Applications ◽

10.1109/csa.2008.61 ◽

2008 ◽

Cited By ~ 3

Author(s):

Kaveh Samiee ◽

GholamAli Rezai Rad

Keyword(s):

Replacement Policy ◽

Cache Performance

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Improving data cache performance with integrated use of split caches, victim cache and stream buffers

10.1145/1152922.1101876 ◽

2004 ◽

Cited By ~ 3

Author(s):

Afrin Naz ◽

Mehran Rezaei ◽

Krishna Kavi ◽

Philip Sweany

Keyword(s):

Data Cache ◽

Cache Performance

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Design of an Intelligent Data Cache with Replacement Policy

International Journal of Embedded and Real-Time Communication Systems ◽

10.4018/ijertcs.2019040106 ◽

2019 ◽

Vol 10 (2) ◽

pp. 87-107

Author(s):

B. Shameedha Begum ◽

N. Ramasubramanian

Keyword(s):

Real Time ◽

Replacement Policy ◽

Data Cache ◽

Cache Performance ◽

Performance Requirements ◽

Novel Approach ◽

Reconfigurable Caches ◽

Real Time Applications ◽

Hard Real Time ◽

Replacement Algorithms

Embedded systems are designed for a variety of applications ranging from Hard Real Time applications to mobile computing, which demands various types of cache designs for better performance. Since real-time applications place stringent requirements on performance, the role of the cache subsystem assumes significance. Reconfigurable caches meet performance requirements under this context. Existing reconfigurable caches tend to use associativity and size for maximizing cache performance. This article proposes a novel approach of a reconfigurable and intelligent data cache (L1) based on replacement algorithms. An intelligent embedded data cache and a dynamic reconfigurable intelligent embedded data cache have been implemented using Verilog 2001 and tested for cache performance. Data collected by enabling the cache with two different replacement strategies have shown that the hit rate improves by 40% when compared to LRU and 21% when compared to MRU for sequential applications which will significantly improve performance of embedded real time application.

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