scholarly journals Fault-tolerant detection of a quantum error

Science ◽  
2018 ◽  
Vol 361 (6399) ◽  
pp. 266-270 ◽  
Author(s):  
S. Rosenblum ◽  
P. Reinhold ◽  
M. Mirrahimi ◽  
Liang Jiang ◽  
L. Frunzio ◽  
...  
Keyword(s):  
Error Detection ◽  
Fault Tolerant ◽  
Critical Component ◽  
Detection Scheme ◽  
Dephasing Time ◽  
Order Of Magnitude ◽  
Quantum Error ◽  
Specific Error ◽  
Logical Qubit

A critical component of any quantum error–correcting scheme is detection of errors by using an ancilla system. However, errors occurring in the ancilla can propagate onto the logical qubit, irreversibly corrupting the encoded information. We demonstrate a fault-tolerant error-detection scheme that suppresses spreading of ancilla errors by a factor of 5, while maintaining the assignment fidelity. The same method is used to prevent propagation of ancilla excitations, increasing the logical qubit dephasing time by an order of magnitude. Our approach is hardware-efficient, as it uses a single multilevel transmon ancilla and a cavity-encoded logical qubit, whose interaction is engineered in situ by using an off-resonant sideband drive. The results demonstrate that hardware-efficient approaches that exploit system-specific error models can yield advances toward fault-tolerant quantum computation.

scholarly journals Exponential suppression of bit or phase errors with cyclic error correction

Nature ◽  
2021 ◽  
Vol 595 (7867) ◽  
pp. 383-387
Author(s):  
◽  
Zijun Chen ◽  
Kevin J. Satzinger ◽  
Juan Atalaya ◽  
Alexander N. Korotkov ◽  
...  
Keyword(s):  
Error Correction ◽  
Error Detection ◽  
Fault Tolerant ◽  
Error Rates ◽  
Quantum Error Correction ◽  
Superconducting Qubits ◽  
Two Dimensional ◽  
Logical Error ◽  
Quantum Error ◽  
Logical Qubit

AbstractRealizing the potential of quantum computing requires sufficiently low logical error rates1. Many applications call for error rates as low as 10−15 (refs. 2–9), but state-of-the-art quantum platforms typically have physical error rates near 10−3 (refs. 10–14). Quantum error correction15–17 promises to bridge this divide by distributing quantum logical information across many physical qubits in such a way that errors can be detected and corrected. Errors on the encoded logical qubit state can be exponentially suppressed as the number of physical qubits grows, provided that the physical error rates are below a certain threshold and stable over the course of a computation. Here we implement one-dimensional repetition codes embedded in a two-dimensional grid of superconducting qubits that demonstrate exponential suppression of bit-flip or phase-flip errors, reducing logical error per round more than 100-fold when increasing the number of qubits from 5 to 21. Crucially, this error suppression is stable over 50 rounds of error correction. We also introduce a method for analysing error correlations with high precision, allowing us to characterize error locality while performing quantum error correction. Finally, we perform error detection with a small logical qubit using the 2D surface code on the same device18,19 and show that the results from both one- and two-dimensional codes agree with numerical simulations that use a simple depolarizing error model. These experimental demonstrations provide a foundation for building a scalable fault-tolerant quantum computer with superconducting qubits.

scholarly journals Logical-qubit operations in an error-detecting surface code

2021 ◽  
Author(s):  
Jorge Marques ◽  
Boris Varbanov ◽  
Miguel Moreira ◽  
Hany Ali ◽  
Nandini Muthusubramanian ◽  
...  
Keyword(s):  
Error Detection ◽  
Fault Tolerant ◽  
The Road ◽  
Logical Operations ◽  
The Difference ◽  
Surface Code ◽  
On The Road ◽  
Qubit Operations ◽  
Quantum Error ◽  
Logical Qubit

Abstract Future fault-tolerant quantum computers will require storing and processing quantum data in logical qubits. We realize a suite of logical operations on a distance-two logical qubit stabilized using repeated error detection cycles. Logical operations include initialization into arbitrary states, measurement in the cardinal bases of the Bloch sphere, and a universal set of single-qubit gates. For each type of operation, we observe higher performance for fault-tolerant variants over non-fault-tolerant variants, and quantify the difference through detailed characterization. In particular, we demonstrate process tomography of logical gates, using the notion of a logical Pauli transfer matrix. This integration of high-fidelity logical operations with a scalable scheme for repeated stabilization is a milestone on the road to quantum error correction with higher-distance superconducting surface codes.

scholarly journals An Efficient Hardware-Based Fault-Tolerant Method for SMS4

2018 ◽  
Vol 208 ◽  
pp. 02005
Author(s):  
Hanguang Luo ◽  
Guangjun Wen ◽  
Jian Su
Keyword(s):  
Error Detection ◽  
Wireless Lan ◽  
Fault Tolerant ◽  
Low Cost ◽  
Primary Objective ◽  
Data Confidentiality ◽  
Detection Scheme ◽  
Detection Delay ◽  
Encryption Decryption ◽  
Online Error Detection

The SMS4 cryptosystem has been used in the Wireless LAN Authentication and Privacy Infrastructure (WAPI) standard for providing data confidentiality in China. So far, reliability has not been considered a primary objective in original version. However, a single fault in the encryption/decryption process can completely change the result of the cryptosystem no matter the natural or malicious injected faults. In this paper, we proposed low-cost structure-independent fault detection scheme for SMS4 cryptosystem which is capable of performing online error detection and can detect a single bit fault or odd multiple bit faults in coverage of 100 percent. Finally, the proposed techniques have been validated on Virtex-7 families FPGA platform to analyze its power consumption, overhead and time delay. It only needs 85 occupied Slices and 8.72mW to run a fault-tolerant scheme of SMS4 cryptosystem with 0.735ns of detection delay. Our new scheme increases in minimum redundancy to enhance cryptosystem’s reliability and achieve a better performance compared with the previous scheme.

scholarly journals Fault-tolerant ancilla preparation and noise threshold lower bounds for the 23-qubit Golay code

2012 ◽  
Vol 12 (11&12) ◽  
pp. 1034-1080
Author(s):  
Adam Paetznick ◽  
Ben W. Reichardt
Keyword(s):  
Error Propagation ◽  
Fault Tolerant ◽  
Error Correcting Code ◽  
Block Size ◽  
Golay Code ◽  
Important Target ◽  
Noise Threshold ◽  
The Cost ◽  
Quantum Error ◽  
Logical Qubit

In fault-tolerant quantum computing schemes, the overhead is often dominated by the cost of preparing codewords reliably. This cost generally increases quadratically with the block size of the underlying quantum error-correcting code. In consequence, large codes that are otherwise very efficient have found limited fault-tolerance applications. Fault-tolerant preparation circuits therefore are an important target for optimization. We study the Golay code, a $23$-qubit quantum error-correcting code that protects the logical qubit to a distance of seven. In simulations, even using a na{\"i}ve ancilla preparation procedure, the Golay code is competitive with other codes both in terms of overhead and the tolerable noise threshold. We provide two simplified circuits for fault-tolerant preparation of Golay code-encoded ancillas. The new circuits minimize error propagation, reducing the overhead by roughly a factor of four compared to standard encoding circuits. By adapting the malignant set counting technique to depolarizing noise, we further prove a threshold above $\threshOverlap$ noise per gate.

scholarly journals Fault-tolerant quantum error detection

2017 ◽  
Vol 3 (10) ◽  
pp. e1701074 ◽  
Author(s):  
Norbert M. Linke ◽  
Mauricio Gutierrez ◽  
Kevin A. Landsman ◽  
Caroline Figgatt ◽  
Shantanu Debnath ◽  
...  
Keyword(s):  
Error Detection ◽  
Fault Tolerant ◽  
Quantum Error

scholarly journals Quantum teleportation of physical qubits into logical code spaces

2021 ◽  
Vol 118 (36) ◽  
pp. e2026250118
Author(s):  
Yi-Han Luo ◽  
Ming-Cheng Chen ◽  
Manuel Erhard ◽  
Han-Sen Zhong ◽  
Dian Wu ◽  
...  
Keyword(s):  
Quantum Information ◽  
Large Scale ◽  
Fault Tolerant ◽  
Quantum Error Correction ◽  
Quantum Circuits ◽  
Entangled State ◽  
Maximally Entangled State ◽  
Universal Quantum ◽  
Quantum Error ◽  
Logical Qubit

Quantum error correction is an essential tool for reliably performing tasks for processing quantum information on a large scale. However, integration into quantum circuits to achieve these tasks is problematic when one realizes that nontransverse operations, which are essential for universal quantum computation, lead to the spread of errors. Quantum gate teleportation has been proposed as an elegant solution for this. Here, one replaces these fragile, nontransverse inline gates with the generation of specific, highly entangled offline resource states that can be teleported into the circuit to implement the nontransverse gate. As the first important step, we create a maximally entangled state between a physical and an error-correctable logical qubit and use it as a teleportation resource. We then demonstrate the teleportation of quantum information encoded on the physical qubit into the error-corrected logical qubit with fidelities up to 0.786. Our scheme can be designed to be fully fault tolerant so that it can be used in future large-scale quantum technologies.

A Flexible Fault Injection Platform for the Analysis of the Symptoms of Soft Errors in FPGA Soft Processors

2017 ◽  
Vol 26 (08) ◽  
pp. 1740009
Author(s):  
Aitzan Sari ◽  
Mihalis Psarakis
Keyword(s):  
Error Detection ◽  
Fault Tolerant ◽  
Fault Injection ◽  
Low Cost ◽  
Soft Errors ◽  
Soft Error ◽  
Detection Scheme ◽  
Detection Techniques ◽  
Error Sensitivity ◽  
Depth Analysis

Due to the high vulnerability of SRAM-based FPGAs in single-event upsets (SEUs), effective fault tolerant soft processor architectures must be considered when we use FPGAs to build embedded systems for critical applications. In the past, the detection of symptoms of soft errors in the behavior of microprocessors has been used for the implementation of low-budget error detection techniques, instead of costly hardware redundancy techniques. To enable the development of such low-cost error detection techniques for FPGA soft processors, we propose an in-depth analysis of the symptoms of SEUs in the FPGA configuration memory. To this end, we present a flexible fault injection platform based on an open-source CAD framework (RapidSmith) for the soft error sensitivity analysis of soft processors in Xilinx SRAM-based FPGAs. Our platform supports the estimation of soft error sensitivity per configuration bit/frame, processor component and benchmark. The fault injection is performed on-chip by a dedicated microcontroller which also monitors processor behavior to identify specific symptoms as consequences of soft errors. The performed analysis showed that these symptoms can be used to build an efficient, low-cost error detection scheme. The proposed platform is demonstrated through an extensive fault injection campaign in the Leon3 soft processor.

On Using Approximate Computing to Build an Error Detection Scheme for Arithmetic Circuits

2020 ◽  
Vol 36 (1) ◽  
pp. 33-46
Author(s):  
B. Deveautour ◽  
A. Virazel ◽  
P. Girard ◽  
V. Gherman
Keyword(s):  
Error Detection ◽  
Arithmetic Circuits ◽  
Approximate Computing ◽  
Detection Scheme

scholarly journals Tunable In Situ 3D-Printed PVDF-TrFE Piezoelectric Arrays

Sensors ◽  
2021 ◽  
Vol 21 (15) ◽  
pp. 5032
Author(s):  
Alec Ikei ◽  
James Wissman ◽  
Kaushik Sampath ◽  
Gregory Yesner ◽  
Syed N. Qadri
Keyword(s):  
3D Printing ◽  
Polyvinylidene Fluoride ◽  
Vinylidene Fluoride ◽  
Mechanical Strain ◽  
Pressure Sensors ◽  
Strain Ratio ◽  
Ex Situ ◽  
Order Of Magnitude ◽  
3D Printed

In the functional 3D-printing field, poly(vinylidene fluoride-co-trifluoroethylene) (PVDF-TrFE) has been shown to be a more promising choice of material over polyvinylidene fluoride (PVDF), due to its ability to be poled to a high level of piezoelectric performance without a large mechanical strain ratio. In this work, a novel presentation of in situ 3D printing and poling of PVDF-TrFE is shown with a d33 performance of up to 18 pC N−1, more than an order of magnitude larger than previously reported in situ poled polymer piezoelectrics. This finding paves the way forward for pressure sensors with much higher sensitivity and accuracy. In addition, the ability of in situ pole sensors to demonstrate different performance levels is shown in a fully 3D-printed five-element sensor array, accelerating and increasing the design space for complex sensing arrays. The in situ poled sample performance was compared to the performance of samples prepared through an ex situ corona poling process.

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