Electronic organ having memory circuit

1979 ◽  
Vol 66 (6) ◽  
pp. 1916-1916
Author(s):  
John W. Robinson ◽  
Stephen L. Howell
Keyword(s):  
Memory Circuit ◽  
Electronic Organ

Brass keyer system for electronic organ

1983 ◽  
Vol 74 (6) ◽  
pp. 1928-1928
Author(s):  
Alan B. Welsh ◽  
John W. Robinson
Keyword(s):  
Electronic Organ

Four-valued memory circuit using three-peak MOS-NDR devices and circuits

2006 ◽  
Vol 42 (9) ◽  
pp. 514 ◽  
Author(s):  
K.-J. Gan ◽  
Y.-H. Chen ◽  
C.-S. Tsai ◽  
L.-X. Su
Keyword(s):  
Memory Circuit

A decoder with OR gates for a Josephson high-density memory circuit

1987 ◽  
Vol 22 (1) ◽  
pp. 85-91 ◽  
Author(s):  
T. Igarashi ◽  
H. Suzuki ◽  
S. Hasuo ◽  
T. Yamaoka
Keyword(s):  
High Density ◽  
Memory Circuit

A Robust and Efficient Compact Model for Phase-Change Memory Circuit Simulations

2021 ◽  
pp. 1-7
Author(s):  
Xuhui Chen ◽  
Feilong Ding ◽  
Xiaoqing Huang ◽  
Xinnan Lin ◽  
Runsheng Wang ◽  
...  
Keyword(s):  
Phase Change ◽  
Phase Change Memory ◽  
Compact Model ◽  
Memory Circuit ◽  
Circuit Simulations ◽  
Change Memory

Large scale integrated circuit chip for an electronic organ

1981 ◽  
Vol 69 (1) ◽  
pp. 338-338
Author(s):  
Harold O. Schwartz ◽  
Dennis E. Kidd
Keyword(s):  
Integrated Circuit ◽  
Large Scale ◽  
Electronic Organ

Automatic bass generator for electronic organ

1987 ◽  
Vol 81 (5) ◽  
pp. 1658-1658
Author(s):  
Stephen L. Howell
Keyword(s):  
Electronic Organ

scholarly journals Beyond the temporal pole: limbic memory circuit in the semantic variant of primary progressive aphasia

Brain ◽  
2014 ◽  
Vol 137 (7) ◽  
pp. 2065-2076 ◽  
Author(s):  
Rachel H. Tan ◽  
Stephanie Wong ◽  
Jillian J. Kril ◽  
Olivier Piguet ◽  
Michael Hornberger ◽  
...  
Keyword(s):  
Primary Progressive Aphasia ◽  
Progressive Aphasia ◽  
Primary Progressive ◽  
Memory Circuit ◽  
Temporal Pole ◽  
Semantic Variant

scholarly journals Demonstration on Ferroelectric-gate Thin Film Transistor NAND-type Array with Disturbance-free Operation

2019 ◽  
Vol 35 (2) ◽  
Author(s):  
Bui Nguyen Quoc Trinh
Keyword(s):  
Thin Film ◽  
Thin Film Transistor ◽  
Sol Gel ◽  
Gate Insulator ◽  
Current Ratio ◽  
Memory State ◽  
Small Loss ◽  
Memory Circuit ◽  
Novel Concept ◽  
Data Reading

Abstract: A novel concept of NAND memory array has been proposed by using only ferroelectric-gate thin film transistors (FGTs), whose structure is constructed from a sol-gel ITO channel and a sol-gel stacked ferroelectric between Bi3.25La0.75Ti3O12 and PbZr0.52TiO0.48O3 (BLT/PZT) gate insulator. Interestingly, ferroelectric cells with a wide memory window of 3 V and a large on/off current ratio of 6 orders, have been successfully integrated in a NAND memory circuit. To protect data writing or reading from disturbance, ferroelectric transistor cells are directly used, instead of paraelectric transistor cells as usual. As a result, we have verified disturbance-free operation for data reading and writing, with a small loss of the memory state and a low power consumption, in principle. Keywords: ITO, PZT, NAND, FeRAM, ferroelectric.

Sign in / Sign up

Export Citation Format

Share Document