Error analysis for digital signal processing of impulsive signals

1977 ◽  
Vol 62 (S1) ◽  
pp. S30-S30
Author(s):  
Curtis I. Holmer
Author(s):  
Minh-Hong Nguyen

This paper presents a low-error, low-area FPGA-based hardware logarithm generator for digital signal processing systems which require high-speed, real time logarithm operations. The proposed logarithm generator employs the modified quasi-symmetrical approach for an efficient hardware implementation. The error analysis and implementation results are also presented and discussed. The achieved results show that the proposed approach can reduce the approximation error and hardware area compared with traditional methods.


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