Circuit simulation for large-scale MOSFET and lossy coupled transmission line circuits using multi-rate iterated timing analysis algorithm

2012 ◽  
Author(s):  
Chun-Jung Chen ◽  
Tien-Hao Shin
2012 ◽  
Vol 433-440 ◽  
pp. 2762-2768
Author(s):  
Chun Jung Chen ◽  
Chih Jen Lee ◽  
Chang Lung Tsai ◽  
Tai Ning Yang ◽  
Allen Y. Chang

Relaxation-based algorithms are efficient in simulating large-scale circuits. One of the Relaxation-based algorithms, ITA (Iterated Timing Analysis), has even been widely used in industry. Hence we present accelerating techniques to fasten ITA’s speed. The basic idea is to let ITA utilize local time steps of subcircuits as much as possible. Our techniques include a heuristic approach, a method based on Strength of Signal Flow, and the method combining the previous two techniques. Proposed methods are quite advantageous, which have been justified by real experiments.


2014 ◽  
Vol 577 ◽  
pp. 636-639
Author(s):  
Chun Jung Chen ◽  
Jenn Dong Sun ◽  
Tai Ning Yang ◽  
Chih Jen Lee

This paper considers utilizing the popular ITA (Iterated Timing Analysis) algorithm in CSM (Combining Simulation Method) to do parallel large-scale circuit simulation. An automatic partitioning method for jobs of CSM is presented, in which the related load balancing issue is also discussed. All proposed methods have been implemented and tested. Experimental results justify pleasing effects of proposed methods.


2011 ◽  
Vol 383-390 ◽  
pp. 2031-2037
Author(s):  
Chun Jung Chen ◽  
Chih Jen Lee ◽  
Chang Lung Tsai ◽  
Allen Y. Chang ◽  
Tien Hao Shih

In this paper, we propose a modified Waveform Relaxation algorithm to perform large-scale circuit simulation for MOSFET circuits containing lossy coupled transmission lines that have been encountered in modern circuit design community, in which a full time-domain transmission line calculation algorithm based on the Method of Characteristic is adopted. New software techniques are proposed to enhance the robustness as well as efficiency of the simulation process. All proposed methods have been implemented and executed to justify the claimed advantages.


2013 ◽  
Vol 748 ◽  
pp. 839-842 ◽  
Author(s):  
Chun Jung Chen ◽  
Yu Wei Chen ◽  
Chang Lung Tsai ◽  
Chih Jen Lee ◽  
Jenn Dong Sun

This paper investigates incremental circuit/sensitivity simulations for large-scale MOSFET circuits using the well-known ITA (Iterated Timing Analysis) algorithm. Incremental simulation uses the result waveforms of previous simulation to fasten the simulation speed, which is quite advantageous in the practical incremental-modifying circuit design strategy. Most proposed methods have been implemented and tested to justify their advantages.


Author(s):  
Chun-Jung Chen ◽  
Chun-Chia Chang ◽  
Chih-Jen Lee ◽  
Chang-Lung Tsai ◽  
Allen Y. Chang ◽  
...  

Sign in / Sign up

Export Citation Format

Share Document