'Intelligent Memory Chips' Give Fully Programmable Synaptic Weights

1989 ◽  
Author(s):  
Steven G. Morton
Keyword(s):  
Intelligent Memory

An intelligent memory transaction engine

1989 ◽  
pp. 286-300
Author(s):  
Abhaya Asthana ◽  
H. V. Jagadish ◽  
Scott C. Knauer
Keyword(s):  
Intelligent Memory

Algorithmic Complexity with Page-Based Intelligent Memory

2000 ◽  
Vol 10 (01) ◽  
pp. 99-109
Author(s):  
Mark Oskin ◽  
Lucian-Vlad Lita ◽  
Frederic T. Chong ◽  
Justin Hensley ◽  
Diana Keen
Keyword(s):  
Linear Time ◽  
Algorithmic Complexity ◽  
Asymptotic Performance ◽  
Problem Size ◽  
Model Of Computation ◽  
Page Size ◽  
Intelligent Memory ◽  
Simulation Results ◽  
Linear Time Algorithms ◽  
The Way

High DRAM densities will make intelligent memory chips a commodity in the next five years [1] [2]. This paper focuses upon a promising model of computation in intelligent memory, Active Pages [3], where computation is associated with each page of memory. Computational hardware scales linearly and inexpensively with data size in this model, reducing the order of many algorithms. This scaling can, for example, reduce linear-time algorithms to [Formula: see text]. When page-based intelligent memory chips become available in commodity, they will change the way programmers select and utilize algorithms. In this paper, we analyze the asymptotic performance of several common algorithms as problem sizes scale. We also derive the optimal page size, as a function of problem size, for each algorithm running with intelligent memory. Finally, we validate these analyses with simulation results.

scholarly journals Programming the FlexRAM parallel intelligent memory system

2003 ◽  
Vol 38 (10) ◽  
pp. 49-60 ◽  
Author(s):  
Basilio B. Fraguela ◽  
Jose Renau ◽  
Paul Feautrier ◽  
David Padua ◽  
Josep Torrellas
Keyword(s):  
Memory System ◽  
Intelligent Memory
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