Digital circuit analysis of insulated shallow extension silicon on void (ISESOV) FET for low voltage applications

2012 ◽  
Author(s):  
Vandana Kumari ◽  
Manoj Saxena ◽  
R. S. Gupta ◽  
Mridula Gupta
Keyword(s):  
Low Voltage ◽  
Digital Circuit ◽  
Circuit Analysis

Digital-circuit analysis of short-gate tunnel FETs for low-voltage applications

2011 ◽  
Vol 26 (8) ◽  
pp. 085001 ◽  
Author(s):  
Jing Zhuge ◽  
Anne S Verhulst ◽  
William G Vandenberghe ◽  
Wim Dehaene ◽  
Ru Huang ◽  
...  
Keyword(s):  
Low Voltage ◽  
Digital Circuit ◽  
Circuit Analysis ◽  
Tunnel Fets

Design of a Digital Baseband Processor for UHF Tags

Electronics ◽  
2021 ◽  
Vol 10 (17) ◽  
pp. 2060
Author(s):  
Na Bai ◽  
Liang Wang ◽  
Yaohua Xu ◽  
Yi Wang
Keyword(s):  
Data Processing ◽  
Low Voltage ◽  
Random Number Generator ◽  
Digital Circuit ◽  
Cmos Process ◽  
Front End ◽  
Rf Front End ◽  
Machine Module ◽  
Baseband Processor ◽  
Digital Baseband

In this paper, we present a new digital baseband processor for UHF tags. It is a low-power and low-voltage digital circuit and adopts the Chinese military standard protocol GJB7377.1. The processor receives data or commands from the RF front-end and carries out various functions, such as receiving and writing data to memory, reading and sending memory data to the RF front-end and killing tags. The processor consists of thirteen main sub-modules: TPP decoding, clock management, random number generator, power management, memory controller, cyclic redundancy check, FM0 encoding, input data processing, output data processing, command detection module, initialization module, state machine module and controller. We use ModelSim for the TPP decoding simulation and communication simulation between tag and reader, and the simulation results meet the design requirements. The processor can be applied to UHF tags and has been taped out using a TSMC 0.18 um CMOS process.

scholarly journals Design of Nanotechnology Based Hazard Free Digital Circuit using Quantum Dot Cellular Automata

2019 ◽  
Vol 9 (1) ◽  
pp. 1207-1210
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Digital Circuits ◽  
Digital Circuit ◽  
Circuit Analysis ◽  
Basic Component ◽  
Quantum Dot Cellular Automata ◽  
Analysis And Design ◽  
Successful Approach

Currently digital circuits have a high flying role in most communications applications. In this Paper, a successful approach to risk-free circuit analysis and design using quantum dot cellular automata is explored at the Nano level. This paper, which we use for both integrated and continuous digital circuits, is a basic component of QCA circuit operation. The Quantum Dot Cellular Automata Designer Tool is very useful for designing a large risk-free circuit. So the proposed risk-free circuit is designed and simulated using this designing software utensil for three input stages. The proposed framework for the risk-free circuit requires only a small number of major gate operations compared to previous structures because of its three input levels.

A TIME-DOMAIN 1.0-V/0.8-MW 6-BIT 125 MS/S FLASH ADC IN 65 NM CMOS

2013 ◽  
Vol 22 (04) ◽  
pp. 1350017 ◽  
Author(s):  
GUANZHONG HUANG ◽  
PINGFEN LIN
Keyword(s):  
Time Domain ◽  
Pulse Width Modulation ◽  
Low Voltage ◽  
Sampling Rate ◽  
Digital Signal ◽  
Input Voltage ◽  
Gray Code ◽  
Digital Circuit ◽  
Cmos Process ◽  
Flash Adc

A 6-bit low-voltage power-efficient flash analog-to-digital converter (ADC) is presented in this paper. The proposed ADC replaces the conventional voltage comparator with a new approach in the time-domain. The reference voltages and the analog input voltage are converted to digital signal in a form of different pulse widths by using a pulse-width-modulation (PWM) circuit. Consequently, the comparison is achieved by checking the sequence of the pulse rising edges rather than amplifying and latching the voltage difference. The total input capacitance of the proposed ADC is as small as tens of femto-farads, resulting in much less demand for the front-end buffer and the sampling switch. In addition, an implementation of the digital foreground calibration helps to get rid of the nonmonotonic comparison thresholds due to mismatch. The calibration operates with the adaptive comparison threshold by tuning the modulation level of the PWM. The intermediate Gray code conversion increases the bubble tolerance by 1LSB. This digital-circuit-heavily-involved ADC has been designed and simulated in a 65 nm CMOS process, achieving 35.24 dB signal-to-noise-and-distortion-ratio (SNDR) at a sampling rate of 125 MS/s while consuming 803 μW from 1 V power supply. As a result, the figure of merit (FoM) is as low as 136 fJ/conversion-step.

Levitation of an Aluminium Disc in a Magnetic Flux Well

2007 ◽  
Vol 44 (3) ◽  
pp. 280-288 ◽  
Author(s):  
N. Barry ◽  
J. Hudgins
Keyword(s):  
Magnetic Flux ◽  
Low Voltage ◽  
Circuit Analysis ◽  
Lifting Force ◽  
Aluminium Disc

An aluminium disc is levitated above a two-coil arrangement in a magnetic flux well, in a low voltage and wattage implementation. A coupled circuit analysis of the system allows an estimate of the lifting force.

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