Symmetry descriptors for Si wafer characterisation for scanning helium atomic beam microscopy mirror

2007 ◽  
Author(s):  
J. Galas ◽  
D. Litwin ◽  
S. Sitarek ◽  
B. Surma ◽  
B. Piatkowski
Keyword(s):  
Atomic Beam ◽  
Si Wafer

Effect of Cu thickness and temperature on growth of graphene on 8-inch Cu/SiO2/Si wafer using cold-wall CVD reactor

2021 ◽  
Vol 42 ◽  
pp. 2948-2952
Author(s):  
Nurhidaya Soriadi ◽  
Mohd Faizol Abdullah ◽  
Firzalaila Syarina Md Yakin ◽  
Siti Aishah Mohamad Badaruddin ◽  
Mohd Ismahadi Syono
Keyword(s):  
Cold Wall ◽  
Si Wafer

scholarly journals Fabrication of a liquid cell for in situ transmission electron microscopy

Microscopy ◽  
2020 ◽  
Author(s):  
Xiaoguang Li ◽  
Kazutaka Mitsuishi ◽  
Masaki Takeguchi
Keyword(s):  
Electron Microscopy ◽  
Transmission Electron Microscopy ◽  
Cost Effective ◽  
Production Method ◽  
Microscopy Imaging ◽  
Transmission Electron ◽  
In Situ Electron Microscopy ◽  
Liquid Cell ◽  
Si Wafer

Abstract Liquid cell transmission electron microscopy (LCTEM) enables imaging of dynamic processes in liquid with high spatial and temporal resolution. The widely used liquid cell (LC) consists of two stacking microchips with a thin wet sample sandwiched between them. The vertically overlapped electron-transparent membrane windows on the microchips provide passage for the electron beam. However, microchips with imprecise dimensions usually cause poor alignment of the windows and difficulty in acquiring high-quality images. In this study, we developed a new and efficient microchip fabrication process for LCTEM with a large viewing area (180 µm × 40 µm) and evaluated the resultant LC. The new positioning reference marks on the surface of the Si wafer dramatically improve the precision of dicing the wafer, making it possible to accurately align the windows on two stacking microchips. The precise alignment led to a liquid thickness of 125.6 nm close to the edge of the viewing area. The performance of our LC was demonstrated by in situ transmission electron microscopy imaging of the dynamic motions of 2-nm Pt particles. This versatile and cost-effective microchip production method can be used to fabricate other types of microchips for in situ electron microscopy.

scholarly journals Silica Layer Used in Sensor Fabrication from a Low-Temperature Silane-Free Procedure

Chemosensors ◽  
2021 ◽  
Vol 9 (2) ◽  
pp. 32
Author(s):  
Pei-Cheng Jiang ◽  
Yu-Ting Chow ◽  
Chi-Wei Chien ◽  
Cheng-Hsun-Tony Chang ◽  
Chii-Ruey Lin
Keyword(s):  
Room Temperature ◽  
Chemical Vapor ◽  
Industrial Safety ◽  
Silica Layer ◽  
Silica Films ◽  
Sensor Fabrication ◽  
Vapor Deposition Technique ◽  
Safety Design ◽  
Biogenic Polyamines ◽  
Si Wafer

Silica (SiO2, silicon dioxide—a dielectric layer commonly used in electronic devices) is widely used in many types of sensors, such as gas, molecular, and biogenic polyamines. To form silica films, core shell or an encapsulated layer, silane has been used as a precursor in recent decades. However, there are many hazards caused by using silane, such as its being extremely flammable, the explosive air, and skin and eye pain. To avoid these hazards, it is necessary to spend many resources on industrial safety design. Thus, the silica synthesized without silane gas which can be determined as a silane-free procedure presents a clean and safe solution to manufactures. In this report, we used the radio frequency (rf = 13.56 MHz) plasma-enhanced chemical vapor deposition technique (PECVD) to form a silica layer at room temperature. The silica layer is formed in hydrogen-based plasma at room temperature and silane gas is not used in this process. The substrate temperature dominates the silica formation, but the distance between the substrate and electrode (DSTE) and the methane additive can enhance the formation of a silica layer on the Si wafer. This silane-free procedure, at room temperature, is not only safer and friendlier to the environment but is also useful in the fabrication of many types of sensors.

scholarly journals Discrete-step evaporation of an atomic beam

2005 ◽  
Vol 33 (1) ◽  
pp. 67-75 ◽  
Author(s):  
T. Lahaye ◽  
D. Gu�ry-Odelin
Keyword(s):  
Atomic Beam ◽  
Discrete Step

scholarly journals E/D-Mode GaN Inverter on a 150-mm Si Wafer Based on p-GaN Gate E-Mode HEMT Technology

Micromachines ◽  
2021 ◽  
Vol 12 (6) ◽  
pp. 617
Author(s):  
Li-Fang Jia ◽  
Lian Zhang ◽  
Jin-Ping Xiao ◽  
Zhe Cheng ◽  
De-Feng Lin ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Room Temperature ◽  
Supply Voltage ◽  
High Input ◽  
Smart Power ◽  
Input Noise ◽  
Power Integrated Circuit ◽  
Different Temperatures ◽  
Device Technology ◽  
Si Wafer

AlGaN/GaN E/D-mode GaN inverters are successfully fabricated on a 150-mm Si wafer. P-GaN gate technology is applied to be compatible with the commercial E-mode GaN power device technology platform and a systematic study of E/D-mode GaN inverters has been conducted with detail. The key electrical characters have been analyzed from room temperature (RT) to 200 °C. Small variations of the inverters are observed at different temperatures. The logic swing voltage of 2.91 V and 2.89 V are observed at RT and 200 °C at a supply voltage of 3 V. Correspondingly, low/high input noise margins of 0.78 V/1.67 V and 0.68 V/1.72 V are observed at RT and 200 °C. The inverters also demonstrate small rising edge time of the output signal. The results show great potential for GaN smart power integrated circuit (IC) application.

Low Dark Current and High Responsivity 1020nm InGaAs/GaAs Nano-Ridge Waveguide Photodetector Monolithically Integrated on a 300-mm Si Wafer

2021 ◽  
pp. 1-1
Author(s):  
Cenk Ibrahim Ozdemir ◽  
Yannick De Koninck ◽  
Didit Yudistira ◽  
Nadezda Kuznetsova ◽  
Marina Baryshnikova ◽  
...  
Keyword(s):  
Dark Current ◽  
Ridge Waveguide ◽  
High Responsivity ◽  
Monolithically Integrated ◽  
Si Wafer

Impact of back-grinding-induced damage on Si wafer thinning for three-dimensional integration

2014 ◽  
Vol 53 (5S2) ◽  
pp. 05GE04 ◽  
Author(s):  
Yoriko Mizushima ◽  
Youngsuk Kim ◽  
Tomoji Nakamura ◽  
Ryuichi Sugie ◽  
Hideki Hashimoto ◽  
...  
Keyword(s):  
Three Dimensional ◽  
Wafer Thinning ◽  
Si Wafer
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