IIA: a novel method to optimize media instruction set of embedded processor

2006 ◽  
Author(s):  
Keming Chen ◽  
Guojun Yu ◽  
Peng Liu ◽  
Qingdong Yao
Keyword(s):  
Instruction Set ◽  
Embedded Processor ◽  
Novel Method

Enhancing a 32-Bit Processor Core with Efficient Cryptographic Instructions

2015 ◽  
Vol 24 (10) ◽  
pp. 1550158 ◽  
Author(s):  
Noura Benhadjyoussef ◽  
Wajih Elhadjyoussef ◽  
Mohsen Machhout ◽  
Rached Tourki ◽  
Kholdoun Torki
Keyword(s):  
Power Consumption ◽  
Random Number ◽  
Random Number Generator ◽  
Instruction Set ◽  
Embedded Processor ◽  
Processor Core ◽  
Cryptographic Algorithms ◽  
Instruction Set Extensions ◽  
Types Of Instruction ◽  
Constrained Devices

Embedded processor is often expected to achieve a higher security with good performance and economical use of resource. However, the choice regarding the best solution for how cryptographic algorithms are incorporated in processor core is one of the most challenging assignments a designer has to face. This paper presents an inexpensive instruction set extensions (ISE) of efficient cryptographic algorithms on 32-bit processors assuring various types of instruction (public/private key cryptography, random number generator (RNG) and secure hash function (SHF)). These extensions provide hardware instructions that implement a full algorithm in a single instruction. Our enhanced LEON2 SPARC V8 core with cryptographic ISE is implemented using Xilinx XC5VFX70t FPGA device and an ASIC CMOS 40-nm technology. The total area of the resulting chip is about 1.93 mm2 and the estimated power consumption of the chip is 16.3 mW at 10 MHz. Hardware cost and power consumption evaluation are provided for different clock frequencies and the achieved results show that our circuit is able to be arranged in many security constrained devices.

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