Taking the X Architecture to the 65-nm technology node

2004 ◽  
Author(s):  
Robin C. Sarma ◽  
Michael C. Smayling ◽  
Narain Arora ◽  
Toshiyuki Nagata ◽  
Michael P. Duane ◽  
...  
Keyword(s):  
Technology Node ◽  
X Architecture

Manufacturability of the X Architecture at the 90-nm technology node

2004 ◽  
Author(s):  
Michael C. Smayling ◽  
Robin C. Sarma ◽  
Toshiyuki Nagata ◽  
Narain Arora ◽  
Michael P. Duane ◽  
...  
Keyword(s):  
Technology Node ◽  
X Architecture

Root Cause Analysis for Pin Leakage

2016 ◽  
Author(s):  
Zhigang Song ◽  
Jochonia Nxumalo ◽  
Manuel Villalobos ◽  
Sweta Pendyala
Keyword(s):  
Failure Analysis ◽  
Root Cause Analysis ◽  
Advanced Technology ◽  
Process Step ◽  
Cause Analysis ◽  
Hard Mask ◽  
Technology Node ◽  
Root Cause ◽  
Tools And Techniques

Abstract Pin leakage continues to be on the list of top yield detractors for microelectronics devices. It is simply manifested as elevated current with one pin or several pins during pin continuity test. Although many techniques are capable to globally localize the fault of pin leakage, root cause analysis and identification for it are still very challenging with today’s advanced failure analysis tools and techniques. It is because pin leakage can be caused by any type of defect, at any layer in the device and at any process step. This paper presents a case study to demonstrate how to combine multiple techniques to accurately identify the root cause of a pin leakage issue for a device manufactured using advanced technology node. The root cause was identified as under-etch issue during P+ implantation hard mask opening for ESD protection diode, causing P+ implantation missing, which was responsible for the nearly ohmic type pin leakage.

scholarly journals CDM Protection Test Structure for I/O Cells in a Submicronic Technology

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 443
Author(s):  
Mihaela-Daniela Dobre ◽  
Philippe Coll ◽  
Gheorghe Brezeanu
Keyword(s):  
Electrostatic Discharge ◽  
New Technology ◽  
Test Chip ◽  
Technology Node ◽  
Ground Resistance ◽  
Maximum Resistance ◽  
Device Model ◽  
Protection Method ◽  
Esd Protection ◽  
Protection Devices

This paper proposes an investigation of a CDM (charge device model) electrostatic discharge (ESD) protection method used in submicronic input–output (I/O) structures. The modeling of the commonly used ESD protection devices as well as the modeling of the breakdown caused by ESD is not accurate using traditional commercial tools, hence the need for test-chip implementation, whenever a new technology node is used in production. The proposed method involves defining, implementing, testing, and concluding on one test-chip structure named generically “CDM ground resistance”. The structure assesses the maximum ground resistance allowed for the considered technology for which CDM protection is assured. The findings are important because they will be actively used as CDM protection for all I/O structures developed in the considered submicronic technology node. The paper will conclude on the constraints in terms of maximum resistance of ground metal track allowed to be CDM protected.

Electrical Masking Improvement with Standard Logic Cell Synthesis Using 45 nm Technology Node

2020 ◽  
Author(s):  
Semiu A. Olowogemo ◽  
Ahmed Yiwere ◽  
Bor-Tyng Lin ◽  
Hao Qiu ◽  
William H. Robinson ◽  
...  
Keyword(s):  
Technology Node ◽  
Cell Synthesis

Advanced CD Linearity Improvement for Multi-Project Wafers and SoC at 95 nm Technology Node

2002 ◽  
Author(s):  
Jeremy Lu ◽  
Nicole L. Sandlin ◽  
Hidetoshi Sato ◽  
Colbert Lu ◽  
Nicole Cheng ◽  
...  
Keyword(s):  
Technology Node ◽  
Linearity Improvement

Metrology Requirements for the 32 nm Technology Node and Beyond

2019 ◽  
Vol 18 (1) ◽  
pp. 151-160
Author(s):  
John Allgair ◽  
Benjamin Bunday ◽  
Aaron Cordes ◽  
Pete Lipscomb ◽  
Milt Godwin ◽  
...  
Keyword(s):  
Technology Node

Performance evaluation of CNFET based operational amplifier at technology node beyond 45-nm

2013 ◽  
Author(s):  
Mohd. Ajmal Kafeel ◽  
Mohd. Hasan ◽  
Mohd. Shah Alam ◽  
A. Kumar ◽  
S. Prasad ◽  
...  
Keyword(s):  
Performance Evaluation ◽  
Operational Amplifier ◽  
Technology Node

Extension of graybeam writing for the 130-nm technology node

1999 ◽  
Author(s):  
Jan M. Chabala ◽  
Frank E. Abboud ◽  
Charles A. Sauer ◽  
Suzanne Weaver ◽  
Maiying Lu ◽  
...  
Keyword(s):  
Technology Node

Microstructural void environment characterization by electron imaging in 45nm technology node to link electromigration and copper microstructure

2013 ◽  
Vol 106 ◽  
pp. 168-171 ◽  
Author(s):  
R. Galand ◽  
G. Brunetti ◽  
L. Arnaud ◽  
J.-L. Rouvière ◽  
L. Clément ◽  
...  
Keyword(s):  
Technology Node ◽  
Electron Imaging
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