Parallel turbo decoder using a low-latency Max-Log-MAP kernel for a VLIW DSP

2001 ◽  
Author(s):  
Yingtao Jiang ◽  
Jun Ma ◽  
Ali Saidi ◽  
Yuke Wang
Keyword(s):  
Low Latency ◽  
Turbo Decoder ◽  
Vliw Dsp ◽  
Log Map

scholarly journals Efficient MAP-algorithm implementation on programmable architectures

2003 ◽  
Vol 1 ◽  
pp. 259-263 ◽  
Author(s):  
F. Kienle ◽  
H. Michel ◽  
F. Gilbert ◽  
N. Wehn
Keyword(s):  
Turbo Codes ◽  
Communication Systems ◽  
Building Blocks ◽  
Communication Performance ◽  
Channel Decoding ◽  
Turbo Decoder ◽  
Decoding Algorithms ◽  
Map Algorithm ◽  
Algorithm Implementation ◽  
Log Map

Abstract. Maximum-A-Posteriori (MAP) decoding algorithms are important HW/SW building blocks in advanced communication systems due to their ability to provide soft-output informations which can be efficiently exploited in iterative channel decoding schemes like Turbo-Codes. Multi-standards demand flexible implementations on programmable platforms. In this paper we analyze a quantized turbo-decoder based on a Max-Log-MAP algorithm with Extrinsic Scaling Factor (ESF). Its communication performance approximate to a Turbo-Decoder with a Log-MAP algorithm and is less sensitive to quantization effects. We present Turbo-Decoder implementations on state-of-the-art DSPs and show that only a Max-Log-MAP implementation fulfills a throughput requirement of ~2 Mbit/s. The negligible overhead for the ESF implementation strengthen the use of Max-Log-MAP with ESF implementation on programmable platforms.

scholarly journals Simplified Log-MAP Algorithm for Very Low-Complexity Turbo Decoder Hardware Architectures

2014 ◽  
Vol 63 (3) ◽  
pp. 531-537 ◽  
Author(s):  
Maurizio Martina ◽  
Stylianos Papaharalabos ◽  
P. Takis Mathiopoulos ◽  
Guido Masera
Keyword(s):  
Low Complexity ◽  
Turbo Decoder ◽  
Map Algorithm ◽  
Hardware Architectures ◽  
Log Map
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