Polycrystalline thin-film transistors on plastic substrates

1999 ◽  
Author(s):  
Paul G. Carey ◽  
Patrick M. Smith ◽  
Steven D. Theiss ◽  
Paul Wickboldt ◽  
Thomas W. Sigmon
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Polycrystalline Thin Film ◽  
Plastic Substrates

Characteristics of Indium Tin Zinc Oxide Thin Film Transistors with Plastic Substrates

2018 ◽  
Vol 28 (4) ◽  
pp. 247-253
Author(s):  
Dae-Gyu Yang ◽  
Hyoung-Do Kim ◽  
Jong-Heon Kim ◽  
Hyun-Suk Kim
Keyword(s):  
Thin Film ◽  
Zinc Oxide ◽  
Thin Film Transistors ◽  
Oxide Thin Film ◽  
Zinc Oxide Thin Film ◽  
Plastic Substrates

Improvement of Reliability for Polycrystalline Thin-Film Transistors Using Self-Aligned Fluorinated Silica Glass Spacers

2005 ◽  
Vol 8 (8) ◽  
pp. G209
Author(s):  
Chun-Hao Tu ◽  
Ting-Chang Chang ◽  
Po-Tsun Liu ◽  
Hsiao-Wen Zan ◽  
Ya-Hsiang Tai ◽  
...  
Keyword(s):  
Thin Film ◽  
Silica Glass ◽  
Thin Film Transistors ◽  
Polycrystalline Thin Film

Cross-linked poly(hydroxy imide) gate-insulating materials for low-temperature processing of organic thin-film transistors

2018 ◽  
Vol 6 (48) ◽  
pp. 13359-13366 ◽  
Author(s):  
Joo-Young Kim ◽  
Ji Whan Kim ◽  
Eun Kyung Lee ◽  
Jeong-Il Park ◽  
Bang-Lin Lee ◽  
...  
Keyword(s):  
Thin Film ◽  
Low Temperature ◽  
Breakdown Voltage ◽  
Thin Film Transistors ◽  
Organic Thin Film Transistors ◽  
Organic Thin Film ◽  
Insulating Materials ◽  
Plastic Substrates ◽  
Insulating Material ◽  
Low Temperature Processing

This paper reports a polymeric gate insulating material of poly(hydroxy imide) cured at the low temperature of 130 °C for the application to organic thin-film transistors on plastic substrates exhibiting high breakdown voltage and no hysteresis.

Low-Temperature Cross-Linking Benzocyclobutene Based Polymer Dielectric for Organic Thin Film Transistors on Plastic Substrates

2019 ◽  
Vol 85 (1) ◽  
pp. 277-283 ◽  
Author(s):  
Rawad K. Hallani ◽  
Maximilian Moser ◽  
Helen Bristow ◽  
Maud V. C. Jenart ◽  
Hendrik Faber ◽  
...  
Keyword(s):  
Thin Film ◽  
Low Temperature ◽  
Thin Film Transistors ◽  
Organic Thin Film Transistors ◽  
Cross Linking ◽  
Organic Thin Film ◽  
Plastic Substrates ◽  
Polymer Dielectric

Simulation of Thermal Transport in Nanowire Composites for Macro-Electronics Applications

2004 ◽  
Author(s):  
Satish Kumar ◽  
Jayathi Y. Murthy ◽  
M. A. Alam
Keyword(s):  
Thin Film ◽  
Biot Number ◽  
Thermal Transport ◽  
Thin Film Transistors ◽  
Finite Volume Scheme ◽  
Temperature Profiles ◽  
Number Density ◽  
Plastic Substrates ◽  
Self Heating ◽  
Fourier Theory

Thermal transport in thin film transistors (TFTs) composed of nanowires embedded in plastic substrates is considered. Random ensembles of intersecting and contacting wires embedded in a substrate are analyzed using Fourier theory. Heat generation due to self-heating is included. A finite volume scheme is used to obtain the temperature solutions in the wires and substrate. Temperature profiles in the ensemble are investigated as a function of wire number density, wire-contact Biot number as well as the Biot number for heat transfer to the substrate.

Thin Film Transistors on Plastic Substrates Using Silicon Deposited by Microwave ECR-CVD

2003 ◽  
Vol 769 ◽  
Author(s):  
Lihong Teng ◽  
Wayne A. Anderson
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Field Effect ◽  
Silicon Films ◽  
Subthreshold Swing ◽  
Field Effect Mobility ◽  
Current Ratio ◽  
Saturation Field ◽  
Plastic Substrates

AbstractThe properties of thin film transistors (TFT's) on plastic substrates with active silicon films deposited by microwave ECR-CVD were studied. Two types of plastic were used, PEEK and polyimide. The a-Si:H TFT deposited at 200°C on polyimide substrates showed a saturation field effect mobility of 4.5 cm2/V-s, a threshold voltage of 3.7 V, a subthreshold swing of 0.69 V/dec and an ON/OFF current ratio of 7.9×106, while the TFT fabricated on PEEK at 200°C showed a saturation field effect mobility of 3.9 cm2/V-s, a threshold voltage of 4.1 V, a subthreshold swing of 0.73 V/dec and an ON/OFF current ratio of 4×106. Comparison is made to TFT's with the Si deposited at 400°C on glass.

High mobility poly-Ge thin-film transistors fabricated on flexible plastic substrates at temperatures below 130°C

2004 ◽  
Vol 33 (4) ◽  
pp. 353-357 ◽  
Author(s):  
D. Shahrjerdi ◽  
B. Hekmatshoar ◽  
S. S. Mohajerzadeh ◽  
A. Khakifirooz ◽  
M. Robertson
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
High Mobility ◽  
Plastic Substrates

A printable form of silicon for high performance thin film transistors on plastic substrates

2004 ◽  
Vol 84 (26) ◽  
pp. 5398-5400 ◽  
Author(s):  
E. Menard ◽  
K. J. Lee ◽  
D.-Y. Khang ◽  
R. G. Nuzzo ◽  
J. A. Rogers
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
High Performance ◽  
Plastic Substrates

Self-aligned Amorphous Silicon Thin Film Transistors with Mobility above 1 cm2V−1s−1fabricated at 300°C on Clear Plastic Substrates

2008 ◽  
Vol 1066 ◽  
Author(s):  
Kunigunde H Cherenack ◽  
Alex Z Kattamis ◽  
Bahman Hekmatshoar ◽  
James C Sturm ◽  
Sigurd Wagner
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Fabrication Process ◽  
Plastic Substrate ◽  
Silicon Thin Film ◽  
Free Standing ◽  
Plastic Substrates ◽  
Effective Mobility ◽  
Clear Plastic

ABSTRACTWe have developed a fabrication process for amorphous-silicon thin-film transistors (a-Si:H TFTs) on free-standing clear plastic substrates at temperatures up to 300°C. The 300°C fabrication process is made possible by using a unique clear plastic substrate that has a very low coefficient of thermal expansion (CTE < 10ppm/°C) and a glass transition temperature higher than 300°C. Our TFTs have a conventional inverted-staggered gate back-channel passivated geometry, which we designed to achieve two goals: accurate overlay alignment and a high effective mobility. A requirement that becomes particularly difficult to meet in the making of TFT backplanes on plastic foil at 300°C is minimizing overlay misalignment. Even though we use a substrate that has a relatively low CTE, accurately aligning the TFTs on the free-standing, 70-micrometer thick substrate is challenging. To deal with this immediate challenge, and to continue developing processes for free-standing web substrates, we are introducing techniques for self-alignment to our TFT fabrication process. We have self-aligned the channel to the gate by exposing through the clear plastic substrate. To raise the effective mobility of our TFTs we reduced the series resistance by decreasing the thickness of the amorphous silicon layer between the source-drain contacts and the accumulation layer in the channel. The back-channel passivated structure allows us to decrease the thickness of the a-Si:H active layer down to around 20nm. These changes have enabled us to raise the effective field effect mobility on clear plastic to values above 1 cm2V−1s−1

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