Modelling and implementation of an ultrasound beamformer system based on DSP builder

2021 ◽  
Author(s):  
Jonathan de Oliveira ◽  
Amauri Amorin Assef ◽  
Matheus Jose da Silva Ruzyk ◽  
Joaquim Miguel Maia ◽  
Mauren Abreu de Souza
Keyword(s):  
Dsp Builder

scholarly journals The Design of Nonlinear Chirp Based on the DSP Builder Technique

2017 ◽  
Vol 128 ◽  
pp. 04009
Author(s):  
Dong Zhang ◽  
Shou-liang Yang ◽  
Yang Zhang
Keyword(s):  
Dsp Builder

BLDC motor commutation based on DSP builder for FPGA

2016 ◽  
Author(s):  
Jose Cervantes ◽  
Erick Cordova ◽  
Angel Israel Soto Marrufo ◽  
Israel Ulises Ponce Monarrez ◽  
Manuel Nandayapa
Keyword(s):  
Bldc Motor ◽  
Dsp Builder

Design and Implementation of FPGA-Based Digital PID Controller Using Distributed Arithmetic

2012 ◽  
Vol 433-440 ◽  
pp. 5659-5665
Author(s):  
Xian Hai Wang ◽  
Jin Ling Jia ◽  
Guang Jian Cheng ◽  
Hai Jun Zhang ◽  
Wen Jun Yu
Keyword(s):  
Processing Speed ◽  
Pid Controller ◽  
Step Response ◽  
Pid Controllers ◽  
Distributed Arithmetic ◽  
Design And Implementation ◽  
Dsp Builder ◽  
Digital Pid ◽  
Quartus Ii ◽  
Field Programmable

This paper proposes a modularized method for the design and implementation of digital PID controller using DA algorithm based on Field Programmable Gate Array (FPGA) device. It is higher integration, lower power consumption, higher processing speed and more convenient reconfiguration compared with PID controllers based on software. The PID controller is modeled by using Simulink and DSP Builder to generate a system model. The controller coefficients are tuned conveniently by simulink and then pre-written into Look-up Tables(LUTs) in model of the proposed PID controller. After modeling, the simulation wave of step response for proposed PID controller is obtained easily by simulink. And the model of digital PID based on DA is then compiled by using Signal Compiler tool in DSP Builder provided by ALTERA corporation and synthesized by using QUARTUS II platform, and then the created file is downloaded into ALTERA’s FPGA device to implement the proposed PID controller.

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