Acceleration method for source mask optimization at 7nm technology node

2021 ◽  
Author(s):  
Xiaojing Su ◽  
Lisong Dong ◽  
Yunyun Hao ◽  
Yajuan Su ◽  
Yayi Wei
Keyword(s):  
Technology Node ◽  
Acceleration Method

Dynamic Behavior Analysis of the Slider Crank Linkage using ANSYS Workbench and MATLAB Program

2013 ◽  
Vol 1 (1) ◽  
pp. 42-25
Author(s):  
Nabil N. Swadi
Keyword(s):  
Graphical Method ◽  
Joint Torque ◽  
Pressure Force ◽  
Matlab Program ◽  
Element Simulation ◽  
Acceleration Method ◽  
Complete Revolution ◽  
Two Phases ◽  
Good Agreement ◽  
Ansys Workbench

This paper is concerned with the study of the kinematic and kinetic analysis of a slider crank linkage using D'Alembert's principle. The links of the considered mechanism are assumed to be rigid. The analytical solution to observe the motion (displacement, velocity, and acceleration), reactions at each joint, torque required to drive the mechanism and the shaking force have been computed by a computer program written in MATLAB language over one complete revolution of the crank shaft. The results are compared with a finite element simulation carried out by using ANSYS Workbench software and are found to be in good agreement. A graphical method (relative velocity and acceleration method) has been also applied for two phases of the crank shaft (q2 = 10° and 130°). The results obtained from this method (graphical) are compared with those obtained from analytical and numerical method and are found very acceptable. To make the analysis linear the friction force on the joints and sliding interface are neglected. All results, in this work, are obtained when the crank shaft turns at a uniform angular velocity (w2 = 188.5 rad/s) and time dependent gas pressure force on the slider crown.

Root Cause Analysis for Pin Leakage

2016 ◽  
Author(s):  
Zhigang Song ◽  
Jochonia Nxumalo ◽  
Manuel Villalobos ◽  
Sweta Pendyala
Keyword(s):  
Failure Analysis ◽  
Root Cause Analysis ◽  
Advanced Technology ◽  
Process Step ◽  
Cause Analysis ◽  
Hard Mask ◽  
Technology Node ◽  
Root Cause ◽  
Tools And Techniques

Abstract Pin leakage continues to be on the list of top yield detractors for microelectronics devices. It is simply manifested as elevated current with one pin or several pins during pin continuity test. Although many techniques are capable to globally localize the fault of pin leakage, root cause analysis and identification for it are still very challenging with today’s advanced failure analysis tools and techniques. It is because pin leakage can be caused by any type of defect, at any layer in the device and at any process step. This paper presents a case study to demonstrate how to combine multiple techniques to accurately identify the root cause of a pin leakage issue for a device manufactured using advanced technology node. The root cause was identified as under-etch issue during P+ implantation hard mask opening for ESD protection diode, causing P+ implantation missing, which was responsible for the nearly ohmic type pin leakage.

scholarly journals A Revisit to CMFD Schemes: Fourier Analysis and Enhancement

Energies ◽  
2021 ◽  
Vol 14 (2) ◽  
pp. 424
Author(s):  
Dean Wang ◽  
Zuolong Zhu
Keyword(s):  
Fourier Analysis ◽  
Eigenvalue Problems ◽  
Neutron Transport ◽  
Coarse Mesh ◽  
Successive Overrelaxation ◽  
Computational Cell ◽  
Artificial Diffusion ◽  
Acceleration Method ◽  
The Stability ◽  
Partial Current

The coarse-mesh finite difference (CMFD) scheme is a very effective nonlinear diffusion acceleration method for neutron transport calculations. CMFD can become unstable and fail to converge when the computational cell optical thickness is relatively large in k-eigenvalue problems or diffusive fixed-source problems. Some variants and fixups have been developed to enhance the stability of CMFD, including the partial current-based CMFD (pCMFD), optimally diffusive CMFD (odCMFD), and linear prolongation-based CMFD (lpCMFD). Linearized Fourier analysis has proven to be a very reliable and accurate tool to investigate the convergence rate and stability of such coupled high-order transport/low-order diffusion iterative schemes. It is shown in this paper that the use of different transport solvers in Fourier analysis may have some potential implications on the development of stabilizing techniques, which is exemplified by the odCMFD scheme. A modification to the artificial diffusion coefficients of odCMFD is proposed to improve its stability. In addition, two explicit expressions are presented to calculate local optimal successive overrelaxation (SOR) factors for lpCMFD to further enhance its acceleration performance for fixed-source problems and k-eigenvalue problems, respectively.

scholarly journals CDM Protection Test Structure for I/O Cells in a Submicronic Technology

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 443
Author(s):  
Mihaela-Daniela Dobre ◽  
Philippe Coll ◽  
Gheorghe Brezeanu
Keyword(s):  
Electrostatic Discharge ◽  
New Technology ◽  
Test Chip ◽  
Technology Node ◽  
Ground Resistance ◽  
Maximum Resistance ◽  
Device Model ◽  
Protection Method ◽  
Esd Protection ◽  
Protection Devices

This paper proposes an investigation of a CDM (charge device model) electrostatic discharge (ESD) protection method used in submicronic input–output (I/O) structures. The modeling of the commonly used ESD protection devices as well as the modeling of the breakdown caused by ESD is not accurate using traditional commercial tools, hence the need for test-chip implementation, whenever a new technology node is used in production. The proposed method involves defining, implementing, testing, and concluding on one test-chip structure named generically “CDM ground resistance”. The structure assesses the maximum ground resistance allowed for the considered technology for which CDM protection is assured. The findings are important because they will be actively used as CDM protection for all I/O structures developed in the considered submicronic technology node. The paper will conclude on the constraints in terms of maximum resistance of ground metal track allowed to be CDM protected.

Electrical Masking Improvement with Standard Logic Cell Synthesis Using 45 nm Technology Node

2020 ◽  
Author(s):  
Semiu A. Olowogemo ◽  
Ahmed Yiwere ◽  
Bor-Tyng Lin ◽  
Hao Qiu ◽  
William H. Robinson ◽  
...  
Keyword(s):  
Technology Node ◽  
Cell Synthesis

Advanced CD Linearity Improvement for Multi-Project Wafers and SoC at 95 nm Technology Node

2002 ◽  
Author(s):  
Jeremy Lu ◽  
Nicole L. Sandlin ◽  
Hidetoshi Sato ◽  
Colbert Lu ◽  
Nicole Cheng ◽  
...  
Keyword(s):  
Technology Node ◽  
Linearity Improvement
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